Lines Matching +full:0 +full:xfcfe3000
32 #clock-cells = <0>;
43 ranges = <0 0 0x18000000>;
48 #size-cells = <0>;
50 cpu@0 {
53 reg = <0>;
62 #clock-cells = <0>;
65 clock-frequency = <0>;
69 #clock-cells = <0>;
77 #clock-cells = <0>;
86 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
90 #clock-cells = <0>;
93 clock-frequency = <0>;
97 #clock-cells = <0>;
100 clock-frequency = <0>;
113 reg = <0x3ffff000 0x1000>;
123 reg = <0xe8007000 64>;
137 reg = <0xe8007800 64>;
151 reg = <0xe8008000 64>;
165 reg = <0xe8008800 64>;
179 reg = <0xe8009000 64>;
193 reg = <0xe8009800 64>;
207 reg = <0xe800a000 64>;
221 reg = <0xe800a800 64>;
235 reg = <0xe800c800 0x24>;
244 #size-cells = <0>;
250 reg = <0xe800d000 0x24>;
259 #size-cells = <0>;
265 reg = <0xe800d800 0x24>;
274 #size-cells = <0>;
280 reg = <0xe800e000 0x24>;
289 #size-cells = <0>;
295 reg = <0xe800e800 0x24>;
304 #size-cells = <0>;
310 reg = <0xe8010000 0x1a0>;
320 reg = <0xe8207000 0x1a0>;
330 reg = <0xe804c800 0x80>;
343 reg = <0xe804e000 0x100>;
359 reg = <0xe804e800 0x100>;
376 #address-cells = <0>;
378 reg = <0xe8201000 0x1000>,
379 <0xe8202000 0x1000>;
384 reg = <0xe8203000 0x800>,
385 <0xe8204800 0x200>;
391 #size-cells = <0>;
396 reg = <0xe8210000 0x3000>;
406 reg = <0xfcfe0000 0x6>;
416 reg = <0xfcfe0000 0x18>;
419 #power-domain-cells = <0>;
426 reg = <0xfcfe0420 4>;
435 reg = <0xfcfe0424 4>;
448 reg = <0xfcfe0428 4>;
457 reg = <0xfcfe042c 4>;
466 reg = <0xfcfe0430 4>;
475 reg = <0xfcfe0434 4>;
484 reg = <0xfcfe0438 4>;
496 reg = <0xfcfe043c 4>;
508 reg = <0xfcfe0444 4>;
520 reg = <0xfcfe3000 0x4230>;
522 port0: gpio-0 {
525 gpio-ranges = <&pinctrl 0 0 6>;
531 gpio-ranges = <&pinctrl 0 16 16>;
537 gpio-ranges = <&pinctrl 0 32 16>;
543 gpio-ranges = <&pinctrl 0 48 16>;
549 gpio-ranges = <&pinctrl 0 64 16>;
555 gpio-ranges = <&pinctrl 0 80 11>;
561 gpio-ranges = <&pinctrl 0 96 16>;
567 gpio-ranges = <&pinctrl 0 112 16>;
573 gpio-ranges = <&pinctrl 0 128 16>;
579 gpio-ranges = <&pinctrl 0 144 8>;
585 gpio-ranges = <&pinctrl 0 160 16>;
591 gpio-ranges = <&pinctrl 0 176 16>;
597 reg = <0xfcfec000 0x30>;
606 reg = <0xfcfec400 0x30>;
615 #size-cells = <0>;
617 reg = <0xfcfee000 0x44>;
636 #size-cells = <0>;
638 reg = <0xfcfee400 0x44>;
657 #size-cells = <0>;
659 reg = <0xfcfee800 0x44>;
678 #size-cells = <0>;
680 reg = <0xfcfeec00 0x44>;
701 #address-cells = <0>;
703 reg = <0xfcfef800 0x6>;
705 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
706 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
707 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
708 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
709 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
710 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
711 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
712 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
713 interrupt-map-mask = <7 0>;
718 reg = <0xfcff0000 0x400>;
729 reg = <0xfcff1000 0x2e>;
743 #clock-cells = <0>;
746 clock-frequency = <0>;