Lines Matching +full:gcc +full:- +full:msm8960
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
8 #include <dt-bindings/mfd/qcom-rpm.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "Qualcomm MSM8960";
15 compatible = "qcom,msm8960";
16 interrupt-parent = <&intc>;
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <19200000>;
23 clock-output-names = "cxo_board";
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <27000000>;
30 clock-output-names = "pxo_board";
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32768>;
37 clock-output-names = "sleep_clk";
41 cpu-pmu {
42 compatible = "qcom,krait-pmu";
44 qcom,no-pc-write;
48 #address-cells = <1>;
49 #size-cells = <0>;
55 enable-method = "qcom,kpss-acc-v1";
57 next-level-cache = <&l2>;
65 enable-method = "qcom,kpss-acc-v1";
67 next-level-cache = <&l2>;
72 l2: l2-cache {
74 cache-level = <2>;
75 cache-unified;
85 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
91 compatible = "qcom,rpm-msm8960";
98 interrupt-names = "ack",
106 qcom,controller-type = "pmic-arbiter";
110 compatible = "qcom,msm8960-qfprom", "qcom,qfprom";
112 #address-cells = <1>;
113 #size-cells = <1>;
119 tsens_backup: backup-calib@414 {
125 compatible = "qcom,msm8960-pinctrl";
127 gpio-controller;
128 gpio-ranges = <&tlmm 0 0 152>;
129 #gpio-cells = <2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
134 i2c1_default_state: i2c1-default-state {
135 i2c1-pins {
138 drive-strength = <8>;
139 bias-disable;
143 i2c1_sleep_state: i2c1-sleep-state {
144 i2c1-pins {
147 drive-strength = <2>;
148 bias-bus-hold;
152 i2c3_default_state: i2c3-default-state {
153 i2c3-pins {
156 drive-strength = <8>;
157 bias-disable;
161 i2c3_sleep_state: i2c3-sleep-state {
162 i2c3-pins {
165 drive-strength = <2>;
166 bias-bus-hold;
170 i2c8_default_state: i2c8-default-state {
171 i2c8-pins {
174 drive-strength = <8>;
175 bias-disable;
179 i2c8_sleep_state: i2c8-sleep-state {
180 i2c8-pins {
183 drive-strength = <2>;
184 bias-bus-hold;
188 i2c10_default_state: i2c10-default-state {
189 i2c10-pins {
192 drive-strength = <8>;
193 bias-disable;
197 i2c10_sleep_state: i2c10-sleep-state {
198 i2c10-pins {
201 drive-strength = <2>;
202 bias-bus-hold;
206 i2c12_default_state: i2c12-default-state {
207 i2c12-pins {
210 drive-strength = <8>;
211 bias-disable;
215 i2c12_sleep_state: i2c12-sleep-state {
216 i2c12-pins {
219 drive-strength = <2>;
220 bias-bus-hold;
224 sdcc3_default_state: sdcc3-default-state {
225 clk-pins {
227 drive-strength = <8>;
228 bias-disable;
231 cmd-pins {
233 drive-strength = <8>;
234 bias-pull-up;
237 data-pins {
239 drive-strength = <8>;
240 bias-pull-up;
244 sdcc3_sleep_state: sdcc3-sleep-state {
245 clk-pins {
247 drive-strength = <2>;
248 bias-disable;
251 cmd-pins {
253 drive-strength = <2>;
254 bias-pull-up;
257 data-pins {
259 drive-strength = <2>;
260 bias-pull-up;
265 gcc: clock-controller@900000 { label
266 compatible = "qcom,gcc-msm8960", "syscon";
268 #clock-cells = <1>;
269 #reset-cells = <1>;
273 clock-names = "cxo",
277 tsens: thermal-sensor {
278 compatible = "qcom,msm8960-tsens";
280 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
281 nvmem-cell-names = "calib", "calib_backup";
283 interrupt-names = "uplow";
286 #thermal-sensor-cells = <1>;
290 intc: interrupt-controller@2000000 {
291 compatible = "qcom,msm-qgic2";
294 interrupt-controller;
295 #interrupt-cells = <3>;
299 compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
300 "qcom,msm-timer";
305 clock-frequency = <27000000>;
307 clock-names = "sleep";
308 cpu-offset = <0x80000>;
311 l2cc: clock-controller@2011000 {
312 compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
314 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
315 clock-names = "pll8_vote", "pxo";
316 #clock-cells = <0>;
319 acc0: clock-controller@2088000 {
320 compatible = "qcom,kpss-acc-v1";
322 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
323 clock-names = "pll8_vote", "pxo";
324 clock-output-names = "acpu0_aux";
325 #clock-cells = <0>;
328 saw0: power-manager@2089000 {
329 compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
333 regulator-min-microvolt = <850000>;
334 regulator-max-microvolt = <1300000>;
338 acc1: clock-controller@2098000 {
339 compatible = "qcom,kpss-acc-v1";
341 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
342 clock-names = "pll8_vote", "pxo";
343 clock-output-names = "acpu1_aux";
344 #clock-cells = <0>;
347 saw1: power-manager@2099000 {
348 compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
352 regulator-min-microvolt = <850000>;
353 regulator-max-microvolt = <1300000>;
357 clock-controller@4000000 {
358 compatible = "qcom,mmcc-msm8960";
360 #clock-cells = <1>;
361 #power-domain-cells = <1>;
362 #reset-cells = <1>;
364 <&gcc PLL3>,
365 <&gcc PLL8_VOTE>,
371 clock-names = "pxo",
384 arm,primecell-periphid = <0x00051180>;
386 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
387 clock-names = "mclk", "apb_pclk";
388 bus-width = <4>;
389 cap-sd-highspeed;
390 cap-mmc-highspeed;
391 max-frequency = <192000000>;
392 no-1-8-v;
393 vmmc-supply = <&vsdcc_fixed>;
395 dma-names = "tx", "rx";
400 sdcc3bam: dma-controller@12182000 {
401 compatible = "qcom,bam-v1.3.0";
404 clocks = <&gcc SDC3_H_CLK>;
405 clock-names = "bam_clk";
406 #dma-cells = <1>;
413 arm,primecell-periphid = <0x00051180>;
415 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
416 clock-names = "mclk", "apb_pclk";
417 bus-width = <8>;
418 max-frequency = <96000000>;
419 non-removable;
420 cap-sd-highspeed;
421 cap-mmc-highspeed;
422 vmmc-supply = <&vsdcc_fixed>;
424 dma-names = "tx", "rx";
429 sdcc1bam: dma-controller@12402000 {
430 compatible = "qcom,bam-v1.3.0";
433 clocks = <&gcc SDC1_H_CLK>;
434 clock-names = "bam_clk";
435 #dma-cells = <1>;
440 compatible = "qcom,gsbi-v1.0.0";
443 cell-index = <12>;
444 clocks = <&gcc GSBI12_H_CLK>;
445 clock-names = "iface";
446 #address-cells = <1>;
447 #size-cells = <1>;
452 compatible = "qcom,i2c-qup-v1.1.1";
454 pinctrl-0 = <&i2c12_default_state>;
455 pinctrl-1 = <&i2c12_sleep_state>;
456 pinctrl-names = "default", "sleep";
458 clocks = <&gcc GSBI12_QUP_CLK>,
459 <&gcc GSBI12_H_CLK>;
460 clock-names = "core",
462 #address-cells = <1>;
463 #size-cells = <0>;
470 compatible = "qcom,ci-hdrc";
474 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
475 clock-names = "core", "iface";
476 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
477 assigned-clock-rates = <60000000>;
478 resets = <&gcc USB_HS1_RESET>;
479 reset-names = "core";
481 ahb-burst-config = <0>;
483 phy-names = "usb-phy";
484 #reset-cells = <1>;
490 compatible = "qcom,usb-hs-phy-msm8960",
491 "qcom,usb-hs-phy";
493 clock-names = "sleep", "ref";
495 reset-names = "por";
496 #phy-cells = <0>;
502 compatible = "qcom,gsbi-v1.0.0";
505 cell-index = <1>;
506 clocks = <&gcc GSBI1_H_CLK>;
507 clock-names = "iface";
508 #address-cells = <1>;
509 #size-cells = <1>;
514 compatible = "qcom,i2c-qup-v1.1.1";
516 pinctrl-0 = <&i2c1_default_state>;
517 pinctrl-1 = <&i2c1_sleep_state>;
518 pinctrl-names = "default", "sleep";
520 clocks = <&gcc GSBI1_QUP_CLK>,
521 <&gcc GSBI1_H_CLK>;
522 clock-names = "core",
524 #address-cells = <1>;
525 #size-cells = <0>;
531 compatible = "qcom,spi-qup-v1.1.1";
533 #address-cells = <1>;
534 #size-cells = <0>;
536 cs-gpios = <&tlmm 8 0>;
537 clocks = <&gcc GSBI1_QUP_CLK>,
538 <&gcc GSBI1_H_CLK>;
539 clock-names = "core",
547 compatible = "qcom,gsbi-v1.0.0";
550 cell-index = <3>;
551 clocks = <&gcc GSBI3_H_CLK>;
552 clock-names = "iface";
553 #address-cells = <1>;
554 #size-cells = <1>;
559 compatible = "qcom,i2c-qup-v1.1.1";
561 pinctrl-0 = <&i2c3_default_state>;
562 pinctrl-1 = <&i2c3_sleep_state>;
563 pinctrl-names = "default", "sleep";
565 clocks = <&gcc GSBI3_QUP_CLK>,
566 <&gcc GSBI3_H_CLK>;
567 clock-names = "core",
569 #address-cells = <1>;
570 #size-cells = <0>;
577 compatible = "qcom,gsbi-v1.0.0";
580 cell-index = <5>;
581 clocks = <&gcc GSBI5_H_CLK>;
582 clock-names = "iface";
583 #address-cells = <1>;
584 #size-cells = <1>;
585 syscon-tcsr = <&tcsr>;
590 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
594 clocks = <&gcc GSBI5_UART_CLK>,
595 <&gcc GSBI5_H_CLK>;
596 clock-names = "core",
604 compatible = "qcom,gsbi-v1.0.0";
607 cell-index = <8>;
608 clocks = <&gcc GSBI8_H_CLK>;
609 clock-names = "iface";
610 #address-cells = <1>;
611 #size-cells = <1>;
612 syscon-tcsr = <&tcsr>;
617 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
621 clocks = <&gcc GSBI8_UART_CLK>,
622 <&gcc GSBI8_H_CLK>;
623 clock-names = "core",
630 compatible = "qcom,i2c-qup-v1.1.1";
632 pinctrl-0 = <&i2c8_default_state>;
633 pinctrl-1 = <&i2c8_sleep_state>;
634 pinctrl-names = "default", "sleep";
636 clocks = <&gcc GSBI8_QUP_CLK>,
637 <&gcc GSBI8_H_CLK>;
638 clock-names = "core",
640 #address-cells = <1>;
641 #size-cells = <0>;
648 compatible = "qcom,gsbi-v1.0.0";
651 cell-index = <10>;
652 clocks = <&gcc GSBI10_H_CLK>;
653 clock-names = "iface";
654 #address-cells = <1>;
655 #size-cells = <1>;
660 compatible = "qcom,i2c-qup-v1.1.1";
662 pinctrl-0 = <&i2c10_default_state>;
663 pinctrl-1 = <&i2c10_sleep_state>;
664 pinctrl-names = "default", "sleep";
666 clocks = <&gcc GSBI10_QUP_CLK>,
667 <&gcc GSBI10_H_CLK>;
668 clock-names = "core",
670 #address-cells = <1>;
671 #size-cells = <0>;
678 compatible = "qcom,tcsr-msm8960", "syscon";
685 clocks = <&gcc PRNG_CLK>;
686 clock-names = "core";
689 lcc: clock-controller@28000000 {
690 compatible = "qcom,lcc-msm8960";
692 #clock-cells = <1>;
693 #reset-cells = <1>;
695 <&gcc PLL4_VOTE>,
702 clock-names = "pxo",
713 thermal-zones {
714 cpu0-thermal {
715 polling-delay-passive = <250>;
716 polling-delay = <1000>;
717 thermal-sensors = <&tsens 0>;
734 cpu1-thermal {
735 polling-delay-passive = <250>;
736 polling-delay = <1000>;
737 thermal-sensors = <&tsens 1>;
756 vsdcc_fixed: vsdcc-regulator {
757 compatible = "regulator-fixed";
758 regulator-name = "SDCC Power";
759 regulator-min-microvolt = <2700000>;
760 regulator-max-microvolt = <2700000>;
761 regulator-always-on;