Lines Matching +full:hsic +full:- +full:state
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
19 * pre-existing /chosen node to be available to insert the
55 #address-cells = <1>;
56 #size-cells = <0>;
58 idle-states {
59 entry-method = "psci";
61 cpu_sleep_wait: cpu-sleep-wait {
62 compatible = "arm,idle-state";
63 arm,psci-suspend-param = <0x0010000>;
64 local-timer-stop;
65 entry-latency-us = <100>;
66 exit-latency-us = <50>;
67 min-residency-us = <1000>;
72 compatible = "arm,cortex-a7";
75 clock-frequency = <792000000>;
76 clock-latency = <61036>; /* two CLK32 periods */
78 cpu-idle-states = <&cpu_sleep_wait>;
79 operating-points-v2 = <&cpu0_opp_table>;
80 #cooling-cells = <2>;
81 nvmem-cells = <&fuse_grade>;
82 nvmem-cell-names = "speed_grade";
86 cpu0_opp_table: opp-table {
87 compatible = "operating-points-v2";
88 opp-shared;
90 opp-792000000 {
91 opp-hz = /bits/ 64 <792000000>;
92 opp-microvolt = <1000000>;
93 clock-latency-ns = <150000>;
94 opp-supported-hw = <0xf>, <0xf>;
98 ckil: clock-cki {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
105 osc: clock-osc {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <24000000>;
109 clock-output-names = "osc";
113 compatible = "usb-nop-xceiv";
115 clock-names = "main_clk";
116 #phy-cells = <0>;
120 compatible = "usb-nop-xceiv";
122 clock-names = "main_clk";
123 power-domains = <&pgc_hsic_phy>;
124 #phy-cells = <0>;
128 compatible = "arm,cortex-a7-pmu";
129 interrupt-parent = <&gpc>;
131 interrupt-affinity = <&cpu0>;
136 * non-configurable replicators don't show up on the
139 compatible = "arm,coresight-static-replicator";
141 out-ports {
142 #address-cells = <1>;
143 #size-cells = <0>;
148 remote-endpoint = <&tpiu_in_port>;
155 remote-endpoint = <&etr_in_port>;
160 in-ports {
163 remote-endpoint = <&etf_out_port>;
170 compatible = "arm,armv7-timer";
171 arm,cpu-registers-not-fw-configured;
172 interrupt-parent = <&intc>;
180 #address-cells = <1>;
181 #size-cells = <1>;
182 compatible = "simple-bus";
183 interrupt-parent = <&gpc>;
187 compatible = "mmio-sram";
190 #address-cells = <1>;
191 #size-cells = <1>;
196 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
199 clock-names = "apb_pclk";
201 ca_funnel_in_ports: in-ports {
202 #address-cells = <1>;
203 #size-cells = <0>;
208 remote-endpoint = <&etm0_out_port>;
215 out-ports {
218 remote-endpoint = <&hugo_funnel_in_port0>;
226 compatible = "arm,coresight-etm3x", "arm,primecell";
230 clock-names = "apb_pclk";
232 out-ports {
235 remote-endpoint = <&ca_funnel_in_port0>;
242 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
245 clock-names = "apb_pclk";
247 in-ports {
248 #address-cells = <1>;
249 #size-cells = <0>;
254 remote-endpoint = <&ca_funnel_out_port0>;
267 out-ports {
270 remote-endpoint = <&etf_in_port>;
277 compatible = "arm,coresight-tmc", "arm,primecell";
280 clock-names = "apb_pclk";
282 in-ports {
285 remote-endpoint = <&hugo_funnel_out_port0>;
290 out-ports {
293 remote-endpoint = <&replicator_in_port0>;
300 compatible = "arm,coresight-tmc", "arm,primecell";
303 clock-names = "apb_pclk";
305 in-ports {
308 remote-endpoint = <&replicator_out_port1>;
315 compatible = "arm,coresight-tpiu", "arm,primecell";
318 clock-names = "apb_pclk";
320 in-ports {
323 remote-endpoint = <&replicator_out_port0>;
329 intc: interrupt-controller@31001000 {
330 compatible = "arm,cortex-a7-gic";
332 #interrupt-cells = <3>;
333 interrupt-controller;
334 interrupt-parent = <&intc>;
342 compatible = "fsl,aips-bus", "simple-bus";
343 #address-cells = <1>;
344 #size-cells = <1>;
349 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
353 gpio-controller;
354 #gpio-cells = <2>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
361 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
365 gpio-controller;
366 #gpio-cells = <2>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
369 gpio-ranges = <&iomuxc 0 13 32>;
373 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
377 gpio-controller;
378 #gpio-cells = <2>;
379 interrupt-controller;
380 #interrupt-cells = <2>;
381 gpio-ranges = <&iomuxc 0 45 29>;
385 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
389 gpio-controller;
390 #gpio-cells = <2>;
391 interrupt-controller;
392 #interrupt-cells = <2>;
393 gpio-ranges = <&iomuxc 0 74 24>;
397 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
401 gpio-controller;
402 #gpio-cells = <2>;
403 interrupt-controller;
404 #interrupt-cells = <2>;
405 gpio-ranges = <&iomuxc 0 98 18>;
409 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
413 gpio-controller;
414 #gpio-cells = <2>;
415 interrupt-controller;
416 #interrupt-cells = <2>;
417 gpio-ranges = <&iomuxc 0 116 23>;
421 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
425 gpio-controller;
426 #gpio-cells = <2>;
427 interrupt-controller;
428 #interrupt-cells = <2>;
429 gpio-ranges = <&iomuxc 0 139 16>;
433 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
440 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
448 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
456 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
464 compatible = "fsl,imx7d-iomuxc-lpsr";
466 fsl,input-sel = <&iomuxc>;
470 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
475 clock-names = "ipg", "per";
479 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
484 clock-names = "ipg", "per";
489 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
494 clock-names = "ipg", "per";
499 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
504 clock-names = "ipg", "per";
509 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
517 compatible = "fsl,imx7d-iomuxc";
521 gpr: iomuxc-gpr@30340000 {
522 compatible = "fsl,imx7d-iomuxc-gpr",
523 "fsl,imx6q-iomuxc-gpr", "syscon",
524 "simple-mfd";
527 mux: mux-controller {
528 compatible = "mmio-mux";
529 #mux-control-cells = <1>;
530 mux-reg-masks = <0x14 0x00000010>;
533 video_mux: csi-mux {
534 compatible = "video-mux";
535 mux-controls = <&mux 0>;
536 #address-cells = <1>;
537 #size-cells = <0>;
548 remote-endpoint = <&mipi_vc0_to_csi_mux>;
556 remote-endpoint = <&csi_from_csi_mux>;
563 #address-cells = <1>;
564 #size-cells = <1>;
565 compatible = "fsl,imx7d-ocotp", "syscon";
573 fuse_grade: fuse-grade@10 {
579 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
580 "syscon", "simple-mfd";
585 reg_1p0d: regulator-vdd1p0d {
586 compatible = "fsl,anatop-regulator";
587 regulator-name = "vdd1p0d";
588 regulator-min-microvolt = <800000>;
589 regulator-max-microvolt = <1200000>;
590 anatop-reg-offset = <0x210>;
591 anatop-vol-bit-shift = <8>;
592 anatop-vol-bit-width = <5>;
593 anatop-min-bit-val = <8>;
594 anatop-min-voltage = <800000>;
595 anatop-max-voltage = <1200000>;
596 anatop-enable-bit = <0>;
599 reg_1p2: regulator-vdd1p2 {
600 compatible = "fsl,anatop-regulator";
601 regulator-name = "vdd1p2";
602 regulator-min-microvolt = <1100000>;
603 regulator-max-microvolt = <1300000>;
604 anatop-reg-offset = <0x220>;
605 anatop-vol-bit-shift = <8>;
606 anatop-vol-bit-width = <5>;
607 anatop-min-bit-val = <0x14>;
608 anatop-min-voltage = <1100000>;
609 anatop-max-voltage = <1300000>;
610 anatop-enable-bit = <0>;
614 compatible = "fsl,imx7d-tempmon";
615 interrupt-parent = <&gpc>;
618 nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
619 nvmem-cell-names = "calib", "temp_grade";
621 #thermal-sensor-cells = <0>;
626 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
629 snvs_rtc: snvs-rtc-lp {
630 compatible = "fsl,sec-v4.0-mon-rtc-lp";
636 clock-names = "snvs-rtc";
639 snvs_poweroff: snvs-poweroff {
640 compatible = "syscon-poweroff";
648 snvs_pwrkey: snvs-powerkey {
649 compatible = "fsl,sec-v4.0-pwrkey";
653 clock-names = "snvs-pwrkey";
655 wakeup-source;
660 clks: clock-controller@30380000 {
661 compatible = "fsl,imx7d-ccm";
665 #clock-cells = <1>;
667 clock-names = "ckil", "osc";
670 src: reset-controller@30390000 {
671 compatible = "fsl,imx7d-src", "syscon";
674 #reset-cells = <1>;
678 compatible = "fsl,imx7d-gpc";
680 interrupt-controller;
682 #interrupt-cells = <3>;
683 interrupt-parent = <&intc>;
686 #address-cells = <1>;
687 #size-cells = <0>;
689 pgc_mipi_phy: power-domain@0 {
690 #power-domain-cells = <0>;
692 power-supply = <®_1p0d>;
695 pgc_pcie_phy: power-domain@1 {
696 #power-domain-cells = <0>;
698 power-supply = <®_1p0d>;
701 pgc_hsic_phy: power-domain@2 {
702 #power-domain-cells = <0>;
704 power-supply = <®_1p2>;
711 compatible = "fsl,aips-bus", "simple-bus";
712 #address-cells = <1>;
713 #size-cells = <1>;
718 compatible = "fsl,imx7d-adc";
722 clock-names = "adc";
723 #io-channel-cells = <1>;
728 compatible = "fsl,imx7d-adc";
732 clock-names = "adc";
733 #io-channel-cells = <1>;
738 #address-cells = <1>;
739 #size-cells = <0>;
740 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
745 clock-names = "ipg", "per";
746 dma-names = "rx", "tx";
752 compatible = "fsl,vf610-ftm-pwm";
754 #pwm-cells = <3>;
756 clock-names = "ftm_sys", "ftm_ext",
766 compatible = "fsl,vf610-ftm-pwm";
768 #pwm-cells = <3>;
770 clock-names = "ftm_sys", "ftm_ext",
780 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
785 clock-names = "ipg", "per";
786 #pwm-cells = <3>;
791 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
796 clock-names = "ipg", "per";
797 #pwm-cells = <3>;
802 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
807 clock-names = "ipg", "per";
808 #pwm-cells = <3>;
813 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
818 clock-names = "ipg", "per";
819 #pwm-cells = <3>;
824 compatible = "fsl,imx7-csi";
828 clock-names = "mclk";
833 remote-endpoint = <&csi_mux_to_csi>;
839 compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif";
844 clock-names = "pix", "axi";
848 mipi_csi: mipi-csi@30750000 {
849 compatible = "fsl,imx7-mipi-csi2";
855 clock-names = "pclk", "wrap", "phy";
856 power-domains = <&pgc_mipi_phy>;
857 phy-supply = <®_1p0d>;
862 #address-cells = <1>;
863 #size-cells = <0>;
873 remote-endpoint = <&csi_mux_from_mipi_vc0>;
880 compatible = "fsl,imx7d-mipi-dsim", "fsl,imx8mm-mipi-dsim";
881 #address-cells = <1>;
882 #size-cells = <0>;
886 clock-names = "bus_clk", "sclk_mipi";
887 assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>,
889 assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>;
890 assigned-clock-rates = <0>, <333000000>;
891 power-domains = <&pgc_mipi_phy>;
893 samsung,burst-clock-frequency = <891000000>;
894 samsung,esc-clock-frequency = <20000000>;
895 samsung,pll-clock-frequency = <24000000>;
901 compatible = "fsl,aips-bus", "simple-bus";
902 #address-cells = <1>;
903 #size-cells = <1>;
907 spba-bus@30800000 {
908 compatible = "fsl,spba-bus", "simple-bus";
909 #address-cells = <1>;
910 #size-cells = <1>;
915 #address-cells = <1>;
916 #size-cells = <0>;
917 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
922 clock-names = "ipg", "per";
923 dma-names = "rx", "tx";
929 #address-cells = <1>;
930 #size-cells = <0>;
931 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
936 clock-names = "ipg", "per";
937 dma-names = "rx", "tx";
943 #address-cells = <1>;
944 #size-cells = <0>;
945 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
950 clock-names = "ipg", "per";
951 dma-names = "rx", "tx";
957 compatible = "fsl,imx7d-uart",
958 "fsl,imx6q-uart";
963 clock-names = "ipg", "per";
968 compatible = "fsl,imx7d-uart",
969 "fsl,imx6q-uart";
974 clock-names = "ipg", "per";
979 compatible = "fsl,imx7d-uart",
980 "fsl,imx6q-uart";
985 clock-names = "ipg", "per";
990 #sound-dai-cells = <0>;
991 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
998 clock-names = "bus", "mclk1", "mclk2", "mclk3";
999 dma-names = "rx", "tx";
1005 #sound-dai-cells = <0>;
1006 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
1013 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1014 dma-names = "rx", "tx";
1020 #sound-dai-cells = <0>;
1021 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
1028 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1029 dma-names = "rx", "tx";
1036 compatible = "fsl,sec-v4.0";
1037 #address-cells = <1>;
1038 #size-cells = <1>;
1044 clock-names = "ipg", "aclk";
1047 compatible = "fsl,sec-v4.0-job-ring";
1053 compatible = "fsl,sec-v4.0-job-ring";
1059 compatible = "fsl,sec-v4.0-job-ring";
1066 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1071 clock-names = "ipg", "per";
1072 fsl,stop-mode = <&gpr 0x10 1>;
1077 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
1082 clock-names = "ipg", "per";
1083 fsl,stop-mode = <&gpr 0x10 2>;
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1090 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1098 #address-cells = <1>;
1099 #size-cells = <0>;
1100 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1118 #address-cells = <1>;
1119 #size-cells = <0>;
1120 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1128 compatible = "fsl,imx7d-uart",
1129 "fsl,imx6q-uart";
1134 clock-names = "ipg", "per";
1139 compatible = "fsl,imx7d-uart",
1140 "fsl,imx6q-uart";
1145 clock-names = "ipg", "per";
1150 compatible = "fsl,imx7d-uart",
1151 "fsl,imx6q-uart";
1156 clock-names = "ipg", "per";
1161 compatible = "fsl,imx7d-uart",
1162 "fsl,imx6q-uart";
1167 clock-names = "ipg", "per";
1172 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1176 #mbox-cells = <2>;
1181 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1185 #mbox-cells = <2>;
1186 fsl,mu-side-b;
1191 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1197 phy-clkgate-delay-us = <400>;
1202 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1208 phy_type = "hsic";
1210 phy-clkgate-delay-us = <400>;
1215 #index-cells = <1>;
1216 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1221 #index-cells = <1>;
1222 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1227 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1233 clock-names = "ipg", "ahb", "per";
1234 bus-width = <4>;
1235 fsl,tuning-step = <2>;
1236 fsl,tuning-start-tap = <20>;
1241 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1247 clock-names = "ipg", "ahb", "per";
1248 bus-width = <4>;
1249 fsl,tuning-step = <2>;
1250 fsl,tuning-start-tap = <20>;
1255 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1261 clock-names = "ipg", "ahb", "per";
1262 bus-width = <4>;
1263 fsl,tuning-step = <2>;
1264 fsl,tuning-start-tap = <20>;
1269 compatible = "fsl,imx7d-qspi";
1271 reg-names = "QuadSPI", "QuadSPI-memory";
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1277 clock-names = "qspi_en", "qspi";
1281 sdma: dma-controller@30bd0000 {
1282 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1287 clock-names = "ipg", "ahb";
1288 #dma-cells = <3>;
1289 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1293 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1295 interrupt-names = "int0", "int1", "int2", "pps";
1305 clock-names = "ipg", "ahb", "ptp",
1307 fsl,num-tx-queues = <3>;
1308 fsl,num-rx-queues = <3>;
1309 fsl,stop-mode = <&gpr 0x10 3>;
1314 dma_apbh: dma-controller@33000000 {
1315 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1321 #dma-cells = <1>;
1322 dma-channels = <4>;
1326 gpmi: nand-controller@33002000 {
1327 compatible = "fsl,imx7d-gpmi-nand";
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1331 reg-names = "gpmi-nand", "bch";
1333 interrupt-names = "bch";
1336 clock-names = "gpmi_io", "gpmi_bch_apb";
1338 dma-names = "rx-tx";
1340 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1341 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;