Lines Matching +full:tegra20 +full:- +full:apbdma
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/nvidia,tegra114-car.h>
8 #include <dt-bindings/soc/tegra-pmc.h>
12 interrupt-parent = <&lic>;
13 #address-cells = <1>;
14 #size-cells = <1>;
22 compatible = "mmio-sram";
24 #address-cells = <1>;
25 #size-cells = <1>;
35 compatible = "nvidia,tegra114-host1x";
39 interrupt-names = "syncpt", "host1x";
41 clock-names = "host1x";
43 reset-names = "host1x", "mc";
46 #address-cells = <1>;
47 #size-cells = <1>;
52 compatible = "nvidia,tegra114-vi";
57 reset-names = "vi";
65 compatible = "nvidia,tegra114-epp";
70 reset-names = "epp";
78 compatible = "nvidia,tegra114-isp";
83 reset-names = "isp";
91 compatible = "nvidia,tegra114-gr2d";
96 reset-names = "2d", "mc";
102 compatible = "nvidia,tegra114-gr3d";
106 reset-names = "3d", "mc";
112 compatible = "nvidia,tegra114-dc";
117 clock-names = "dc", "parent";
119 reset-names = "dc";
131 compatible = "nvidia,tegra114-dc";
136 clock-names = "dc", "parent";
138 reset-names = "dc";
150 compatible = "nvidia,tegra114-hdmi";
155 clock-names = "hdmi", "parent";
157 reset-names = "hdmi";
162 compatible = "nvidia,tegra114-dsi";
167 clock-names = "dsi", "lp", "parent";
169 reset-names = "dsi";
170 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
173 #address-cells = <1>;
174 #size-cells = <0>;
178 compatible = "nvidia,tegra114-dsi";
183 clock-names = "dsi", "lp", "parent";
185 reset-names = "dsi";
186 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
189 #address-cells = <1>;
190 #size-cells = <0>;
194 compatible = "nvidia,tegra114-msenc";
199 reset-names = "mpe";
207 compatible = "nvidia,tegra114-tsec";
219 gic: interrupt-controller@50041000 {
220 compatible = "arm,cortex-a15-gic";
221 #interrupt-cells = <3>;
222 interrupt-controller;
229 interrupt-parent = <&gic>;
232 lic: interrupt-controller@60004000 {
233 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
239 interrupt-controller;
240 #interrupt-cells = <3>;
241 interrupt-parent = <&gic>;
245 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer";
257 compatible = "nvidia,tegra114-car";
259 #clock-cells = <1>;
260 #reset-cells = <1>;
263 flow-controller@60007000 {
264 compatible = "nvidia,tegra114-flowctrl";
268 apbdma: dma@6000a000 { label
269 compatible = "nvidia,tegra114-apbdma";
305 reset-names = "dma";
306 #dma-cells = <1>;
310 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
315 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
325 #gpio-cells = <2>;
326 gpio-controller;
327 #interrupt-cells = <2>;
328 interrupt-controller;
329 gpio-ranges = <&pinmux 0 0 246>;
333 compatible = "nvidia,tegra114-vde";
337 <0x6001c200 0x100>, /* Post-processing Engine */
343 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
347 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
349 interrupt-names = "sync-token", "bsev", "sxe";
351 reset-names = "vde", "mc";
357 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
363 compatible = "nvidia,tegra114-pinmux";
372 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
374 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
377 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
379 reg-shift = <2>;
383 dmas = <&apbdma 8>, <&apbdma 8>;
384 dma-names = "rx", "tx";
389 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
391 reg-shift = <2>;
395 dmas = <&apbdma 9>, <&apbdma 9>;
396 dma-names = "rx", "tx";
401 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
403 reg-shift = <2>;
407 dmas = <&apbdma 10>, <&apbdma 10>;
408 dma-names = "rx", "tx";
413 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
415 reg-shift = <2>;
419 dmas = <&apbdma 19>, <&apbdma 19>;
420 dma-names = "rx", "tx";
425 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
427 #pwm-cells = <2>;
430 reset-names = "pwm";
435 compatible = "nvidia,tegra114-i2c";
438 #address-cells = <1>;
439 #size-cells = <0>;
441 clock-names = "div-clk";
443 reset-names = "i2c";
444 dmas = <&apbdma 21>, <&apbdma 21>;
445 dma-names = "rx", "tx";
450 compatible = "nvidia,tegra114-i2c";
453 #address-cells = <1>;
454 #size-cells = <0>;
456 clock-names = "div-clk";
458 reset-names = "i2c";
459 dmas = <&apbdma 22>, <&apbdma 22>;
460 dma-names = "rx", "tx";
465 compatible = "nvidia,tegra114-i2c";
468 #address-cells = <1>;
469 #size-cells = <0>;
471 clock-names = "div-clk";
473 reset-names = "i2c";
474 dmas = <&apbdma 23>, <&apbdma 23>;
475 dma-names = "rx", "tx";
480 compatible = "nvidia,tegra114-i2c";
483 #address-cells = <1>;
484 #size-cells = <0>;
486 clock-names = "div-clk";
488 reset-names = "i2c";
489 dmas = <&apbdma 26>, <&apbdma 26>;
490 dma-names = "rx", "tx";
495 compatible = "nvidia,tegra114-i2c";
498 #address-cells = <1>;
499 #size-cells = <0>;
501 clock-names = "div-clk";
503 reset-names = "i2c";
504 dmas = <&apbdma 24>, <&apbdma 24>;
505 dma-names = "rx", "tx";
510 compatible = "nvidia,tegra114-spi";
513 #address-cells = <1>;
514 #size-cells = <0>;
516 clock-names = "spi";
518 reset-names = "spi";
519 dmas = <&apbdma 15>, <&apbdma 15>;
520 dma-names = "rx", "tx";
525 compatible = "nvidia,tegra114-spi";
528 #address-cells = <1>;
529 #size-cells = <0>;
531 clock-names = "spi";
533 reset-names = "spi";
534 dmas = <&apbdma 16>, <&apbdma 16>;
535 dma-names = "rx", "tx";
540 compatible = "nvidia,tegra114-spi";
543 #address-cells = <1>;
544 #size-cells = <0>;
546 clock-names = "spi";
548 reset-names = "spi";
549 dmas = <&apbdma 17>, <&apbdma 17>;
550 dma-names = "rx", "tx";
555 compatible = "nvidia,tegra114-spi";
558 #address-cells = <1>;
559 #size-cells = <0>;
561 clock-names = "spi";
563 reset-names = "spi";
564 dmas = <&apbdma 18>, <&apbdma 18>;
565 dma-names = "rx", "tx";
570 compatible = "nvidia,tegra114-spi";
573 #address-cells = <1>;
574 #size-cells = <0>;
576 clock-names = "spi";
578 reset-names = "spi";
579 dmas = <&apbdma 27>, <&apbdma 27>;
580 dma-names = "rx", "tx";
585 compatible = "nvidia,tegra114-spi";
588 #address-cells = <1>;
589 #size-cells = <0>;
591 clock-names = "spi";
593 reset-names = "spi";
594 dmas = <&apbdma 28>, <&apbdma 28>;
595 dma-names = "rx", "tx";
600 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
607 compatible = "nvidia,tegra114-kbc";
612 reset-names = "kbc";
617 compatible = "nvidia,tegra114-pmc";
620 clock-names = "pclk", "clk32k_in";
621 #clock-cells = <1>;
625 compatible = "nvidia,tegra114-efuse";
628 clock-names = "fuse";
630 reset-names = "fuse";
633 mc: memory-controller@70019000 {
634 compatible = "nvidia,tegra114-mc";
637 clock-names = "mc";
641 #reset-cells = <1>;
642 #iommu-cells = <1>;
646 compatible = "nvidia,tegra114-hda", "nvidia,tegra30-hda";
652 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
656 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
661 compatible = "nvidia,tegra114-ahub";
668 clock-names = "d_audio", "apbif";
682 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
685 dmas = <&apbdma 1>, <&apbdma 1>,
686 <&apbdma 2>, <&apbdma 2>,
687 <&apbdma 3>, <&apbdma 3>,
688 <&apbdma 4>, <&apbdma 4>,
689 <&apbdma 6>, <&apbdma 6>,
690 <&apbdma 7>, <&apbdma 7>,
691 <&apbdma 12>, <&apbdma 12>,
692 <&apbdma 13>, <&apbdma 13>,
693 <&apbdma 14>, <&apbdma 14>,
694 <&apbdma 29>, <&apbdma 29>;
695 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
700 #address-cells = <1>;
701 #size-cells = <1>;
704 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
706 nvidia,ahub-cif-ids = <4 4>;
709 reset-names = "i2s";
714 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
716 nvidia,ahub-cif-ids = <5 5>;
719 reset-names = "i2s";
724 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
726 nvidia,ahub-cif-ids = <6 6>;
729 reset-names = "i2s";
734 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
736 nvidia,ahub-cif-ids = <7 7>;
739 reset-names = "i2s";
744 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
746 nvidia,ahub-cif-ids = <8 8>;
749 reset-names = "i2s";
755 compatible = "nvidia,tegra114-mipi";
758 #nvidia,mipi-calibrate-cells = <1>;
762 compatible = "nvidia,tegra114-dfll";
766 <0x70110200 0x100>; /* Look-up table RAM */
771 clock-names = "soc", "ref", "i2c";
773 reset-names = "dvco";
774 #clock-cells = <0>;
775 clock-output-names = "dfllCPU_out";
776 nvidia,droop-ctrl = <0x00000f00>;
777 nvidia,force-mode = <1>;
785 compatible = "nvidia,tegra114-sdhci";
789 clock-names = "sdhci";
791 reset-names = "sdhci";
796 compatible = "nvidia,tegra114-sdhci";
800 clock-names = "sdhci";
802 reset-names = "sdhci";
807 compatible = "nvidia,tegra114-sdhci";
811 clock-names = "sdhci";
813 reset-names = "sdhci";
818 compatible = "nvidia,tegra114-sdhci";
822 clock-names = "sdhci";
824 reset-names = "sdhci";
829 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
835 reset-names = "usb";
840 phy1: usb-phy@7d000000 {
841 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
849 clock-names = "reg", "pll_u", "utmi-pads";
851 reset-names = "usb", "utmi-pads";
852 #phy-cells = <0>;
853 nvidia,hssync-start-delay = <0>;
854 nvidia,idle-wait-delay = <17>;
855 nvidia,elastic-limit = <16>;
856 nvidia,term-range-adj = <6>;
857 nvidia,xcvr-setup = <9>;
858 nvidia,xcvr-lsfslew = <0>;
859 nvidia,xcvr-lsrslew = <3>;
860 nvidia,hssquelch-level = <2>;
861 nvidia,hsdiscon-level = <5>;
862 nvidia,xcvr-hsslew = <12>;
863 nvidia,has-utmi-pad-registers;
869 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
875 reset-names = "usb";
880 phy3: usb-phy@7d008000 {
881 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
889 clock-names = "reg", "pll_u", "utmi-pads";
891 reset-names = "usb", "utmi-pads";
892 #phy-cells = <0>;
893 nvidia,hssync-start-delay = <0>;
894 nvidia,idle-wait-delay = <17>;
895 nvidia,elastic-limit = <16>;
896 nvidia,term-range-adj = <6>;
897 nvidia,xcvr-setup = <9>;
898 nvidia,xcvr-lsfslew = <0>;
899 nvidia,xcvr-lsrslew = <3>;
900 nvidia,hssquelch-level = <2>;
901 nvidia,hsdiscon-level = <5>;
902 nvidia,xcvr-hsslew = <12>;
908 #address-cells = <1>;
909 #size-cells = <0>;
913 compatible = "arm,cortex-a15";
921 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
923 clock-latency = <300000>;
928 compatible = "arm,cortex-a15";
934 compatible = "arm,cortex-a15";
940 compatible = "arm,cortex-a15";
946 compatible = "arm,cortex-a15-pmu";
951 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
955 compatible = "arm,armv7-timer";
965 interrupt-parent = <&gic>;