Lines Matching +full:pcie +full:- +full:x1
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
31 internal-regs {
33 compatible = "marvell,mv88f6810-pinctrl";
37 pcie {
38 compatible = "marvell,armada-370-pcie";
42 #address-cells = <3>;
43 #size-cells = <2>;
45 msi-parent = <&mpic>;
46 bus-range = <0x00 0xff>;
53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
60 /* x1 port */
61 pcie@1,0 {
63 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
65 #address-cells = <3>;
66 #size-cells = <2>;
67 interrupt-names = "intx";
68 interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
69 #interrupt-cells = <1>;
70 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
71 0x81000000 0 0 0x81000000 0x1 0 1 0>;
72 bus-range = <0x00 0xff>;
73 interrupt-map-mask = <0 0 0 7>;
74 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
78 marvell,pcie-port = <0>;
79 marvell,pcie-lane = <0>;
83 pcie1_intc: interrupt-controller {
84 interrupt-controller;
85 #interrupt-cells = <1>;
89 /* x1 port */
90 pcie@2,0 {
92 assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
94 #address-cells = <3>;
95 #size-cells = <2>;
96 interrupt-names = "intx";
97 interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
98 #interrupt-cells = <1>;
101 bus-range = <0x00 0xff>;
102 interrupt-map-mask = <0 0 0 7>;
103 interrupt-map = <0 0 0 1 &pcie2_intc 0>,
107 marvell,pcie-port = <1>;
108 marvell,pcie-lane = <0>;
112 pcie2_intc: interrupt-controller {
113 interrupt-controller;
114 #interrupt-cells = <1>;
118 /* x1 port */
119 pcie@3,0 {
121 assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
123 #address-cells = <3>;
124 #size-cells = <2>;
125 interrupt-names = "intx";
126 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
127 #interrupt-cells = <1>;
130 bus-range = <0x00 0xff>;
131 interrupt-map-mask = <0 0 0 7>;
132 interrupt-map = <0 0 0 1 &pcie3_intc 0>,
136 marvell,pcie-port = <2>;
137 marvell,pcie-lane = <0>;
141 pcie3_intc: interrupt-controller {
142 interrupt-controller;
143 #interrupt-cells = <1>;