Lines Matching +full:pll +full:- +full:periph

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 	#address-cells = <1>;
12 	#size-cells = <1>;
14 	interrupt-parent = <&gic>;
17 		#address-cells = <1>;
18 		#size-cells = <0>;
22 			compatible = "arm,cortex-a7";
24 			next-level-cache = <&L2_0>;
25 			enable-method = "psci";
30 			compatible = "arm,cortex-a7";
32 			next-level-cache = <&L2_0>;
33 			enable-method = "psci";
36 		L2_0: l2-cache0 {
38 			cache-level = <2>;
39 			cache-unified;
44 		compatible = "arm,armv7-timer";
49 		arm,cpu-registers-not-fw-configured;
53 		compatible = "arm,cortex-a7-pmu";
56 		interrupt-affinity = <&CA7_0>, <&CA7_1>;
60 		periph_clk: periph-clk {
61 			compatible = "fixed-clock";
62 			#clock-cells = <0>;
63 			clock-frequency = <200000000>;
66 		hsspi_pll: hsspi-pll {
67 			compatible = "fixed-clock";
68 			#clock-cells = <0>;
69 			clock-frequency = <400000000>;
74 		compatible = "arm,psci-0.2";
79 		compatible = "simple-bus";
80 		#address-cells = <1>;
81 		#size-cells = <1>;
84 		gic: interrupt-controller@1000 {
85 			compatible = "arm,cortex-a7-gic";
86 			#interrupt-cells = <3>;
87 			interrupt-controller;
97 		compatible = "simple-bus";
98 		#address-cells = <1>;
99 		#size-cells = <1>;
103 			compatible = "brcm,bcm6345-uart";
107 			clock-names = "refclk";
112 			#address-cells = <1>;
113 			#size-cells = <0>;
114 			compatible = "brcm,bcm6846-hsspi", "brcm,bcmbca-hsspi-v1.0";
118 			clock-names = "hsspi", "pll";
119 			num-cs = <8>;
123 		nand_controller: nand-controller@1800 {
124 			#address-cells = <1>;
125 			#size-cells = <0>;
126 			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
128 			reg-names = "nand", "nand-int-base";