Lines Matching +full:pll +full:- +full:periph

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 	#address-cells = <1>;
12 	#size-cells = <1>;
14 	interrupt-parent = <&gic>;
17 		#address-cells = <1>;
18 		#size-cells = <0>;
22 			compatible = "brcm,brahma-b15";
24 			next-level-cache = <&L2_0>;
25 			enable-method = "psci";
30 			compatible = "brcm,brahma-b15";
32 			next-level-cache = <&L2_0>;
33 			enable-method = "psci";
36 		L2_0: l2-cache0 {
38 			cache-level = <2>;
39 			cache-unified;
44 		compatible = "arm,armv7-timer";
52 		compatible = "arm,cortex-a15-pmu";
55 		interrupt-affinity = <&B15_0>, <&B15_1>;
59 		periph_clk: periph-clk {
60 			compatible = "fixed-clock";
61 			#clock-cells = <0>;
62 			clock-frequency = <50000000>;
65 		hsspi_pll: hsspi-pll {
66 			compatible = "fixed-clock";
67 			#clock-cells = <0>;
68 			clock-frequency = <400000000>;
73 		compatible = "arm,psci-0.2";
78 		compatible = "simple-bus";
79 		#address-cells = <1>;
80 		#size-cells = <1>;
83 		gic: interrupt-controller@1000 {
84 			compatible = "arm,cortex-a15-gic";
85 			#interrupt-cells = <3>;
86 			interrupt-controller;
97 		compatible = "simple-bus";
98 		#address-cells = <1>;
99 		#size-cells = <1>;
103 			compatible = "brcm,bcm6345-uart";
107 			clock-names = "refclk";
112 			#address-cells = <1>;
113 			#size-cells = <0>;
114 			compatible = "brcm,bcm63148-hsspi", "brcm,bcmbca-hsspi-v1.0";
118 			clock-names = "hsspi", "pll";
119 			num-cs = <8>;
123 		nand_controller: nand-controller@2000 {
124 			#address-cells = <1>;
125 			#size-cells = <0>;
126 			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
128 			reg-names = "nand", "nand-int-base";