Lines Matching +full:sun8i +full:- +full:h3 +full:- +full:ccu
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/sun6i-rtc.h>
44 #include <dt-bindings/clock/sun8i-de2.h>
45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/clock/sun8i-r-ccu.h>
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/reset/sun8i-de2.h>
49 #include <dt-bindings/reset/sun8i-h3-ccu.h>
50 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
58 #address-cells = <1>;
59 #size-cells = <1>;
62 framebuffer-hdmi {
63 compatible = "allwinner,simple-framebuffer",
64 "simple-framebuffer";
65 allwinner,pipeline = "mixer0-lcd0-hdmi";
67 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
71 framebuffer-tve {
72 compatible = "allwinner,simple-framebuffer",
73 "simple-framebuffer";
74 allwinner,pipeline = "mixer1-lcd1-tve";
76 <&ccu CLK_TVE>;
82 #address-cells = <1>;
83 #size-cells = <1>;
86 osc24M: osc24M-clk {
87 #clock-cells = <0>;
88 compatible = "fixed-clock";
89 clock-frequency = <24000000>;
90 clock-accuracy = <50000>;
91 clock-output-names = "osc24M";
94 osc32k: osc32k-clk {
95 #clock-cells = <0>;
96 compatible = "fixed-clock";
97 clock-frequency = <32768>;
98 clock-accuracy = <50000>;
99 clock-output-names = "ext_osc32k";
103 de: display-engine {
104 compatible = "allwinner,sun8i-h3-display-engine";
110 compatible = "simple-bus";
111 #address-cells = <1>;
112 #size-cells = <1>;
113 dma-ranges;
119 clocks = <&ccu CLK_BUS_DE>,
120 <&ccu CLK_DE>;
121 clock-names = "bus",
123 resets = <&ccu RST_BUS_DE>;
124 #clock-cells = <1>;
125 #reset-cells = <1>;
129 compatible = "allwinner,sun8i-h3-de2-mixer-0";
133 clock-names = "bus",
138 #address-cells = <1>;
139 #size-cells = <0>;
145 remote-endpoint = <&tcon0_in_mixer0>;
151 dma: dma-controller@1c02000 {
152 compatible = "allwinner,sun8i-h3-dma";
155 clocks = <&ccu CLK_BUS_DMA>;
156 resets = <&ccu RST_BUS_DMA>;
157 #dma-cells = <1>;
160 tcon0: lcd-controller@1c0c000 {
161 compatible = "allwinner,sun8i-h3-tcon-tv",
162 "allwinner,sun8i-a83t-tcon-tv";
165 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
166 clock-names = "ahb", "tcon-ch1";
167 resets = <&ccu RST_BUS_TCON0>;
168 reset-names = "lcd";
171 #address-cells = <1>;
172 #size-cells = <0>;
178 remote-endpoint = <&mixer0_out_tcon0>;
183 #address-cells = <1>;
184 #size-cells = <0>;
189 remote-endpoint = <&hdmi_in_tcon0>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&mmc0_pins>;
200 resets = <&ccu RST_BUS_MMC0>;
201 reset-names = "ahb";
204 #address-cells = <1>;
205 #size-cells = <0>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&mmc1_pins>;
213 resets = <&ccu RST_BUS_MMC1>;
214 reset-names = "ahb";
217 #address-cells = <1>;
218 #size-cells = <0>;
224 resets = <&ccu RST_BUS_MMC2>;
225 reset-names = "ahb";
228 #address-cells = <1>;
229 #size-cells = <0>;
235 #address-cells = <1>;
236 #size-cells = <1>;
238 ths_calibration: thermal-sensor-calibration@34 {
244 compatible = "allwinner,sun8i-h3-msgbox",
245 "allwinner,sun6i-a31-msgbox";
247 clocks = <&ccu CLK_BUS_MSGBOX>;
248 resets = <&ccu RST_BUS_MSGBOX>;
250 #mbox-cells = <1>;
254 compatible = "allwinner,sun8i-h3-musb";
256 clocks = <&ccu CLK_BUS_OTG>;
257 resets = <&ccu RST_BUS_OTG>;
259 interrupt-names = "mc";
261 phy-names = "usb";
268 compatible = "allwinner,sun8i-h3-usb-phy";
274 reg-names = "phy_ctrl",
279 clocks = <&ccu CLK_USB_PHY0>,
280 <&ccu CLK_USB_PHY1>,
281 <&ccu CLK_USB_PHY2>,
282 <&ccu CLK_USB_PHY3>;
283 clock-names = "usb0_phy",
287 resets = <&ccu RST_USB_PHY0>,
288 <&ccu RST_USB_PHY1>,
289 <&ccu RST_USB_PHY2>,
290 <&ccu RST_USB_PHY3>;
291 reset-names = "usb0_reset",
296 #phy-cells = <1>;
300 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
303 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
304 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
306 phy-names = "usb";
311 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
314 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
315 <&ccu CLK_USB_OHCI0>;
316 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
318 phy-names = "usb";
323 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
326 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
327 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
329 phy-names = "usb";
334 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
337 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
338 <&ccu CLK_USB_OHCI1>;
339 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
341 phy-names = "usb";
346 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
349 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
350 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
352 phy-names = "usb";
357 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
360 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
361 <&ccu CLK_USB_OHCI2>;
362 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
364 phy-names = "usb";
369 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
372 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
373 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
375 phy-names = "usb";
380 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
383 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
384 <&ccu CLK_USB_OHCI3>;
385 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
387 phy-names = "usb";
391 ccu: clock@1c20000 { label
395 clock-names = "hosc", "losc";
396 #clock-cells = <1>;
397 #reset-cells = <1>;
403 interrupt-parent = <&r_intc>;
406 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
408 clock-names = "apb", "hosc", "losc";
409 gpio-controller;
410 #gpio-cells = <3>;
411 interrupt-controller;
412 #interrupt-cells = <3>;
414 csi_pins: csi-pins {
421 emac_rgmii_pins: emac-rgmii-pins {
426 drive-strength = <40>;
429 i2c0_pins: i2c0-pins {
434 i2c1_pins: i2c1-pins {
439 i2c2_pins: i2c2-pins {
444 mmc0_pins: mmc0-pins {
448 drive-strength = <30>;
449 bias-pull-up;
452 mmc1_pins: mmc1-pins {
456 drive-strength = <30>;
457 bias-pull-up;
460 mmc2_8bit_pins: mmc2-8bit-pins {
466 drive-strength = <30>;
467 bias-pull-up;
470 spdif_tx_pin: spdif-tx-pin {
475 spi0_pins: spi0-pins {
480 spi1_pins: spi1-pins {
485 uart0_pa_pins: uart0-pa-pins {
490 uart1_pins: uart1-pins {
495 uart1_rts_cts_pins: uart1-rts-cts-pins {
500 uart2_pins: uart2-pins {
505 uart2_rts_cts_pins: uart2-rts-cts-pins {
510 uart3_pins: uart3-pins {
515 uart3_rts_cts_pins: uart3-rts-cts-pins {
522 compatible = "allwinner,sun8i-a23-timer";
530 compatible = "allwinner,sun8i-h3-emac";
534 interrupt-names = "macirq";
535 resets = <&ccu RST_BUS_EMAC>;
536 reset-names = "stmmaceth";
537 clocks = <&ccu CLK_BUS_EMAC>;
538 clock-names = "stmmaceth";
542 #address-cells = <1>;
543 #size-cells = <0>;
544 compatible = "snps,dwmac-mdio";
547 mdio-mux {
548 compatible = "allwinner,sun8i-h3-mdio-mux";
549 #address-cells = <1>;
550 #size-cells = <0>;
552 mdio-parent-bus = <&mdio>;
555 compatible = "allwinner,sun8i-h3-mdio-internal";
557 #address-cells = <1>;
558 #size-cells = <0>;
560 int_mii_phy: ethernet-phy@1 {
561 compatible = "ethernet-phy-ieee802.3-c22";
563 clocks = <&ccu CLK_BUS_EPHY>;
564 resets = <&ccu RST_BUS_EPHY>;
570 #address-cells = <1>;
571 #size-cells = <0>;
576 mbus: dram-controller@1c62000 {
580 reg-names = "mbus", "dram";
581 clocks = <&ccu CLK_MBUS>,
582 <&ccu CLK_DRAM>,
583 <&ccu CLK_BUS_DRAM>;
584 clock-names = "mbus", "dram", "bus";
585 #address-cells = <1>;
586 #size-cells = <1>;
587 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
588 #interconnect-cells = <1>;
592 compatible = "allwinner,sun8i-h3-spi";
595 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
596 clock-names = "ahb", "mod";
598 dma-names = "rx", "tx";
599 pinctrl-names = "default";
600 pinctrl-0 = <&spi0_pins>;
601 resets = <&ccu RST_BUS_SPI0>;
603 #address-cells = <1>;
604 #size-cells = <0>;
608 compatible = "allwinner,sun8i-h3-spi";
611 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
612 clock-names = "ahb", "mod";
614 dma-names = "rx", "tx";
615 pinctrl-names = "default";
616 pinctrl-0 = <&spi1_pins>;
617 resets = <&ccu RST_BUS_SPI1>;
619 #address-cells = <1>;
620 #size-cells = <0>;
624 compatible = "allwinner,sun6i-a31-wdt";
631 #sound-dai-cells = <0>;
632 compatible = "allwinner,sun8i-h3-spdif";
635 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
636 resets = <&ccu RST_BUS_SPDIF>;
637 clock-names = "apb", "spdif";
639 dma-names = "tx";
644 compatible = "allwinner,sun8i-h3-pwm";
647 #pwm-cells = <3>;
652 #sound-dai-cells = <0>;
653 compatible = "allwinner,sun8i-h3-i2s";
656 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
657 clock-names = "apb", "mod";
659 resets = <&ccu RST_BUS_I2S0>;
660 dma-names = "rx", "tx";
665 #sound-dai-cells = <0>;
666 compatible = "allwinner,sun8i-h3-i2s";
669 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
670 clock-names = "apb", "mod";
672 resets = <&ccu RST_BUS_I2S1>;
673 dma-names = "rx", "tx";
678 #sound-dai-cells = <0>;
679 compatible = "allwinner,sun8i-h3-i2s";
682 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
683 clock-names = "apb", "mod";
685 resets = <&ccu RST_BUS_I2S2>;
686 dma-names = "tx";
691 #sound-dai-cells = <0>;
692 compatible = "allwinner,sun8i-h3-codec";
695 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
696 clock-names = "apb", "codec";
697 resets = <&ccu RST_BUS_CODEC>;
699 dma-names = "rx", "tx";
700 allwinner,codec-analog-controls = <&codec_analog>;
705 compatible = "snps,dw-apb-uart";
708 reg-shift = <2>;
709 reg-io-width = <4>;
710 clocks = <&ccu CLK_BUS_UART0>;
711 resets = <&ccu RST_BUS_UART0>;
713 dma-names = "tx", "rx";
718 compatible = "snps,dw-apb-uart";
721 reg-shift = <2>;
722 reg-io-width = <4>;
723 clocks = <&ccu CLK_BUS_UART1>;
724 resets = <&ccu RST_BUS_UART1>;
726 dma-names = "tx", "rx";
731 compatible = "snps,dw-apb-uart";
734 reg-shift = <2>;
735 reg-io-width = <4>;
736 clocks = <&ccu CLK_BUS_UART2>;
737 resets = <&ccu RST_BUS_UART2>;
739 dma-names = "tx", "rx";
744 compatible = "snps,dw-apb-uart";
747 reg-shift = <2>;
748 reg-io-width = <4>;
749 clocks = <&ccu CLK_BUS_UART3>;
750 resets = <&ccu RST_BUS_UART3>;
752 dma-names = "tx", "rx";
757 compatible = "allwinner,sun6i-a31-i2c";
760 clocks = <&ccu CLK_BUS_I2C0>;
761 resets = <&ccu RST_BUS_I2C0>;
762 pinctrl-names = "default";
763 pinctrl-0 = <&i2c0_pins>;
765 #address-cells = <1>;
766 #size-cells = <0>;
770 compatible = "allwinner,sun6i-a31-i2c";
773 clocks = <&ccu CLK_BUS_I2C1>;
774 resets = <&ccu RST_BUS_I2C1>;
775 pinctrl-names = "default";
776 pinctrl-0 = <&i2c1_pins>;
778 #address-cells = <1>;
779 #size-cells = <0>;
783 compatible = "allwinner,sun6i-a31-i2c";
786 clocks = <&ccu CLK_BUS_I2C2>;
787 resets = <&ccu RST_BUS_I2C2>;
788 pinctrl-names = "default";
789 pinctrl-0 = <&i2c2_pins>;
791 #address-cells = <1>;
792 #size-cells = <0>;
795 gic: interrupt-controller@1c81000 {
796 compatible = "arm,gic-400";
801 interrupt-controller;
802 #interrupt-cells = <3>;
807 compatible = "allwinner,sun8i-h3-csi";
810 clocks = <&ccu CLK_BUS_CSI>,
811 <&ccu CLK_CSI_SCLK>,
812 <&ccu CLK_DRAM_CSI>;
813 clock-names = "bus", "mod", "ram";
814 resets = <&ccu RST_BUS_CSI>;
815 pinctrl-names = "default";
816 pinctrl-0 = <&csi_pins>;
821 compatible = "allwinner,sun8i-h3-dw-hdmi",
822 "allwinner,sun8i-a83t-dw-hdmi";
824 reg-io-width = <1>;
826 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
827 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
828 clock-names = "iahb", "isfr", "tmds", "cec";
829 resets = <&ccu RST_BUS_HDMI1>;
830 reset-names = "ctrl";
832 phy-names = "phy";
836 #address-cells = <1>;
837 #size-cells = <0>;
843 remote-endpoint = <&tcon0_out_hdmi>;
853 hdmi_phy: hdmi-phy@1ef0000 {
854 compatible = "allwinner,sun8i-h3-hdmi-phy";
856 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
857 <&ccu CLK_PLL_VIDEO>;
858 clock-names = "bus", "mod", "pll-0";
859 resets = <&ccu RST_BUS_HDMI0>;
860 reset-names = "phy";
861 #phy-cells = <0>;
867 interrupt-parent = <&r_intc>;
870 clock-output-names = "osc32k", "osc32k-out", "iosc";
872 #clock-cells = <1>;
875 r_intc: interrupt-controller@1f00c00 {
876 compatible = "allwinner,sun8i-h3-r-intc",
877 "allwinner,sun6i-a31-r-intc";
878 interrupt-controller;
879 #interrupt-cells = <3>;
885 compatible = "allwinner,sun8i-h3-r-ccu";
888 <&ccu CLK_PLL_PERIPH0>;
889 clock-names = "hosc", "losc", "iosc", "pll-periph";
890 #clock-cells = <1>;
891 #reset-cells = <1>;
894 codec_analog: codec-analog@1f015c0 {
895 compatible = "allwinner,sun8i-h3-codec-analog";
900 compatible = "allwinner,sun6i-a31-ir";
902 clock-names = "apb", "ir";
910 compatible = "allwinner,sun6i-a31-i2c";
913 pinctrl-names = "default";
914 pinctrl-0 = <&r_i2c_pins>;
918 #address-cells = <1>;
919 #size-cells = <0>;
923 compatible = "snps,dw-apb-uart";
926 reg-shift = <2>;
927 reg-io-width = <4>;
930 pinctrl-names = "default";
931 pinctrl-0 = <&r_uart_pins>;
936 compatible = "allwinner,sun8i-h3-r-pinctrl";
938 interrupt-parent = <&r_intc>;
942 clock-names = "apb", "hosc", "losc";
943 gpio-controller;
944 #gpio-cells = <3>;
945 interrupt-controller;
946 #interrupt-cells = <3>;
948 r_ir_rx_pin: r-ir-rx-pin {
953 r_i2c_pins: r-i2c-pins {
958 r_pwm_pin: r-pwm-pin {
963 r_uart_pins: r-uart-pins {
970 compatible = "allwinner,sun8i-h3-pwm";
972 pinctrl-names = "default";
973 pinctrl-0 = <&r_pwm_pin>;
975 #pwm-cells = <3>;