Lines Matching +full:message +full:- +full:based
1 .. SPDX-License-Identifier: GPL-2.0
9 -----------------------
11 For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2
23 0x10 Inbound Message Register 0
24 0x14 Inbound Message Register 1
25 0x18 Outbound Message Register 0
26 0x1C Outbound Message Register 1
36 For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:
41 0x10 Inbound Message Register 0
42 0x14 Inbound Message Register 1
43 0x18 Outbound Message Register 0
44 0x1C Outbound Message Register 1
54 For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
72 0x10 Inbound Message Register
73 0x14 Outbound Message Register
74 0x40-0x1040 Inbound Queue
75 0x1040-0x2040 Outbound Queue
78 For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
100 0x10400 PCIe Function 0 to CPU Message A
101 0x10420 CPU to PCIe Function 0 Message A
108 ----------------------------------------
115 - Get a free request packet by reading the inbound queue port or
121 Requests allocated in host memory must be aligned on 32-bytes boundary.
123 - Fill the packet.
125 - Post the packet to IOP by writing it to inbound queue. For requests
130 - The IOP process the request. When the request is completed, it
139 flag is set in the request, the low 32-bit context value will be
142 - The host read the outbound queue and complete the request.
147 Non-queued requests (reset/flush etc) can be sent via inbound message
148 register 0. An outbound message with the same value indicates the completion
149 of an inbound message.
153 ------------------------------------
159 - Allocate a free request in host DMA coherent memory.
161 Requests allocated in host memory must be aligned on 32-bytes boundary.
163 - Fill the request with index of the request in the flag.
171 - Post the inbound list writer pointer to IOP.
173 - The IOP process the request. When the request is completed, the flag of
174 the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a
179 - The host read the outbound list copy pointer shadow register and compare
186 Non-queued requests (reset communication/reset/flush etc) can be sent via PCIe
187 Function 0 to CPU Message A register. The CPU to PCIe Function 0 Message register
188 with the same value indicates the completion of message.
191 User-level Interface
192 ---------------------
199 driver-version R driver version string
200 firmware-version R firmware version string
204 -----------------------------------------------------------------------------
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213 linux@highpoint-tech.com
215 http://www.highpoint-tech.com