Lines Matching +full:qcom +full:- +full:sm8450 +full:- +full:lpass +full:- +full:state
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8450 SoC LPASS LPI TLMM
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
18 const: qcom,sm8450-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
27 - description: LPASS Core voting clock
28 - description: LPASS Audio voting clock
30 clock-names:
32 - const: core
33 - const: audio
36 "-state$":
38 - $ref: "#/$defs/qcom-sm8450-lpass-state"
39 - patternProperties:
40 "-pins$":
41 $ref: "#/$defs/qcom-sm8450-lpass-state"
45 qcom-sm8450-lpass-state:
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
59 pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
76 - $ref: qcom,lpass-lpi-common.yaml#
79 - compatible
80 - reg
81 - clocks
82 - clock-names
87 - |
88 #include <dt-bindings/sound/qcom,q6afe.h>
90 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
95 clock-names = "core", "audio";
96 gpio-controller;
97 #gpio-cells = <2>;
98 gpio-ranges = <&lpi_tlmm 0 0 23>;
100 wsa-swr-active-state {
101 clk-pins {
104 drive-strength = <2>;
105 slew-rate = <1>;
106 bias-disable;
109 data-pins {
112 drive-strength = <2>;
113 slew-rate = <1>;
117 tx-swr-sleep-clk-state {
120 drive-strength = <2>;
121 bias-pull-down;