Lines Matching +full:usb +full:- +full:phy
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,rcar-gen2-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen2 USB PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,usb-phy-r8a7742 # RZ/G1H
17 - renesas,usb-phy-r8a7743 # RZ/G1M
18 - renesas,usb-phy-r8a7744 # RZ/G1N
19 - renesas,usb-phy-r8a7745 # RZ/G1E
20 - renesas,usb-phy-r8a77470 # RZ/G1C
21 - renesas,usb-phy-r8a7790 # R-Car H2
22 - renesas,usb-phy-r8a7791 # R-Car M2-W
23 - renesas,usb-phy-r8a7794 # R-Car E2
24 - const: renesas,rcar-gen2-usb-phy # R-Car Gen2 or RZ/G1
29 '#address-cells':
32 '#size-cells':
38 clock-names:
40 - const: usbhs
42 power-domains:
49 "^usb-phy@[02]$":
51 description: Subnode corresponding to a USB channel.
58 '#phy-cells':
60 The phandle's argument in the PHY specifier is the USB controller
61 selector for the USB channel.
63 - 0 for EHCI/OHCI
64 - 1 for HS-USB
66 - 0 for PCI EHCI/OHCI
67 - 1 for HS-USB (channel 0) or xHCI (channel 2)
71 - reg
72 - '#phy-cells'
77 - compatible
78 - reg
79 - '#address-cells'
80 - '#size-cells'
81 - clocks
82 - clock-names
83 - resets
84 - power-domains
85 - usb-phy@0
91 const: renesas,usb-phy-r8a77470
94 usb-phy@2: false
97 - usb-phy@2
102 - |
103 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
104 #include <dt-bindings/power/r8a7790-sysc.h>
105 usb-phy-controller@e6590100 {
106 compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy";
108 #address-cells = <1>;
109 #size-cells = <0>;
111 clock-names = "usbhs";
112 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
115 usb0: usb-phy@0 {
117 #phy-cells = <1>;
119 usb2: usb-phy@2 {
121 #phy-cells = <1>;