Lines Matching +full:phy +full:- +full:output +full:- +full:clock
1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR803x PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
19 - if:
24 - ethernet-phy-id004d.d0c0
29 const: 7 # This PHY is always at MDIO address 7 in the IPQ5018 SoC
33 - description:
34 GE PHY MISC reset which triggers a reset across MDC, DSP, RX, and TX lines.
36 qcom,dac-preset-short-cable:
38 Set if this phy is connected to another phy to adjust the values for
41 If not set, DAC values are not modified and it is assumed the MDI output pins
42 of this PHY are directly connected to an RJ45 connector.
48 - ethernet-phy-id004d.d0c0
50 qca,clk-out-frequency:
51 description: Clock output frequency in Hertz.
55 qca,clk-out-strength:
56 description: Clock output driver strength.
60 qca,disable-smarteee:
64 qca,keep-pll-enabled:
67 want to use the clock output without an ethernet link.
72 qca,disable-hibernation-mode:
75 that the hardware of PHY will not enter power saving mode when the
77 valid clock.
80 qca,smarteee-tw-us-100m:
86 qca,smarteee-tw-us-1g:
92 vddio-supply:
96 The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
97 either connect this to the vddio-regulator (1.5V / 1.8V) or the
98 vddh-regulator (2.5V).
102 vddio-regulator:
109 vddh-regulator:
112 Dummy subnode to model the external connection of the PHY VDDH
120 - |
121 #include <dt-bindings/net/qca-ar803x.h>
124 #address-cells = <1>;
125 #size-cells = <0>;
127 phy-mode = "rgmii-id";
129 ethernet-phy@0 {
132 qca,clk-out-frequency = <125000000>;
133 qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
135 vddio-supply = <&vddio>;
137 vddio: vddio-regulator {
138 regulator-min-microvolt = <1800000>;
139 regulator-max-microvolt = <1800000>;
143 - |
144 #include <dt-bindings/net/qca-ar803x.h>
147 #address-cells = <1>;
148 #size-cells = <0>;
150 phy-mode = "rgmii-id";
152 ethernet-phy@0 {
155 qca,clk-out-frequency = <50000000>;
156 qca,keep-pll-enabled;
158 vddio-supply = <&vddh>;
160 vddh: vddh-regulator {
164 - |
165 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
168 #address-cells = <1>;
169 #size-cells = <0>;
171 ge_phy: ethernet-phy@7 {
172 compatible = "ethernet-phy-id004d.d0c0";