Lines Matching +full:has +full:- +full:legacy +full:- +full:mode
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
21 Each phy has at most 3 LEDs connected and can be declared
27 - enum:
28 - qca,qca8327
29 - qca,qca8328
30 - qca,qca8334
31 - qca,qca8337
33 qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
34 qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
35 qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
36 qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
41 reset-gpios:
46 qca,ignore-power-on-sel:
49 Ignore power-on pin strapping to configure LED open-drain or EEPROM
51 the OEM has decided not to use pin strapping and falls back to SW regs.
53 qca,led-open-drain:
56 Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
58 OEM does not use pin strapping to set this mode and prefers to set it
59 using SW regs. The pin strappings related to LED open-drain mode are
66 If this is not present, the legacy mapping is used and the
68 With the legacy mapping the reg corresponding to the internal
69 mdio is the switch reg with an offset of -1.
74 "^(ethernet-)?ports$":
78 "^(ethernet-)?port@[0-6]$":
82 $ref: dsa-port.yaml#
85 qca,sgmii-rxclk-falling-edge:
91 qca,sgmii-txclk-falling-edge:
96 qca,sgmii-enable-pll:
109 - required:
110 - ports
111 - required:
112 - ethernet-ports
115 - compatible
116 - reg
121 - |
122 #include <dt-bindings/gpio/gpio.h>
123 #include <dt-bindings/leds/common.h>
126 #address-cells = <1>;
127 #size-cells = <0>;
129 external_phy_port1: ethernet-phy@0 {
133 external_phy_port2: ethernet-phy@1 {
137 external_phy_port3: ethernet-phy@2 {
141 external_phy_port4: ethernet-phy@3 {
145 external_phy_port5: ethernet-phy@4 {
151 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
155 #address-cells = <1>;
156 #size-cells = <0>;
161 phy-mode = "rgmii";
163 fixed-link {
165 full-duplex;
172 phy-handle = <&external_phy_port1>;
178 phy-handle = <&external_phy_port2>;
184 phy-handle = <&external_phy_port3>;
190 phy-handle = <&external_phy_port4>;
196 phy-handle = <&external_phy_port5>;
201 - |
202 #include <dt-bindings/gpio/gpio.h>
205 #address-cells = <1>;
206 #size-cells = <0>;
210 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
214 #address-cells = <1>;
215 #size-cells = <0>;
220 phy-mode = "rgmii";
222 fixed-link {
224 full-duplex;
231 phy-mode = "internal";
232 phy-handle = <&internal_phy_port1>;
235 #address-cells = <1>;
236 #size-cells = <0>;
242 default-state = "keep";
249 default-state = "keep";
257 phy-mode = "internal";
258 phy-handle = <&internal_phy_port2>;
264 phy-mode = "internal";
265 phy-handle = <&internal_phy_port3>;
271 phy-mode = "internal";
272 phy-handle = <&internal_phy_port4>;
278 phy-mode = "internal";
279 phy-handle = <&internal_phy_port5>;
285 phy-mode = "sgmii";
287 qca,sgmii-rxclk-falling-edge;
289 fixed-link {
291 full-duplex;
297 #address-cells = <1>;
298 #size-cells = <0>;
300 internal_phy_port1: ethernet-phy@0 {
304 internal_phy_port2: ethernet-phy@1 {
308 internal_phy_port3: ethernet-phy@2 {
312 internal_phy_port4: ethernet-phy@3 {
316 internal_phy_port5: ethernet-phy@4 {