Lines Matching +full:async +full:- +full:page +full:- +full:mode
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl172.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
18 - arm,pl172
19 - arm,pl175
20 - arm,pl176
22 - compatible
27 - enum:
28 - arm,pl172
29 - arm,pl175
30 - arm,pl176
31 - const: arm,primecell
36 '#address-cells':
39 '#size-cells':
47 clock-names:
49 - const: mpmcclk
50 - const: apb_pclk
52 clock-ranges: true
58 "^cs[0-9]$":
62 "^flash@[0-9],[0-9a-f]+$":
64 $ref: /schemas/mtd/mtd-physmap.yaml#
67 "^(gpio|sram)@[0-9],[0-9a-f]+$":
72 '#address-cells':
75 '#size-cells':
83 clock-ranges: true
91 mpmc,memory-width:
97 mpmc,async-page-mode:
100 Enable asynchronous page mode.
102 mpmc,cs-active-high:
107 mpmc,byte-lane-low:
112 mpmc,extended-wait:
117 mpmc,buffer-enable:
123 mpmc,write-protect:
128 mpmc,read-enable-delay:
134 mpmc,write-enable-delay:
140 mpmc,output-enable-delay:
146 mpmc,write-access-delay:
152 mpmc,read-access-delay:
158 mpmc,page-mode-read-delay:
161 Delay for asynchronous page mode sequential
164 mpmc,turn-round-delay:
171 - compatible
172 - reg
173 - '#address-cells'
174 - '#size-cells'
175 - ranges
176 - clocks
177 - clock-names
182 - |
183 #include <dt-bindings/clock/lpc18xx-ccu.h>
185 memory-controller@40005000 {
189 clock-names = "mpmcclk", "apb_pclk";
190 #address-cells = <2>;
191 #size-cells = <1>;
198 #address-cells = <2>;
199 #size-cells = <1>;
203 mpmc,memory-width = <16>;
204 mpmc,byte-lane-low;
205 mpmc,write-enable-delay = <0>;
206 mpmc,output-enable-delay = <0>;
207 mpmc,read-enable-delay = <70>;
208 mpmc,page-mode-read-delay = <70>;
211 compatible = "sst,sst39vf320", "cfi-flash";
213 bank-width = <2>;
214 #address-cells = <1>;
215 #size-cells = <1>;