Lines Matching +full:sun8i +full:- +full:h3 +full:- +full:ccu

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Chen-Yu Tsai <wens@csie.org>
11   - Maxime Ripard <mripard@kernel.org>
14   "#phy-cells":
19       - allwinner,sun8i-a83t-hdmi-phy
20       - allwinner,sun8i-h3-hdmi-phy
21       - allwinner,sun8i-r40-hdmi-phy
22       - allwinner,sun50i-a64-hdmi-phy
23       - allwinner,sun50i-h6-hdmi-phy
31       - description: Bus Clock
32       - description: Module Clock
33       - description: Parent of the PHY clock
34       - description: Second possible parent of the PHY clock
36   clock-names:
39       - const: bus
40       - const: mod
41       - const: pll-0
42       - const: pll-1
47   reset-names:
51   - compatible
52   - reg
53   - clocks
54   - clock-names
55   - resets
56   - reset-names
63           - allwinner,sun8i-r40-hdmi-phy
70     clock-names:
79             - allwinner,sun8i-h3-hdmi-phy
80             - allwinner,sun50i-a64-hdmi-phy
87       clock-names:
95       clock-names:
101   - |
102     #include <dt-bindings/clock/sun8i-a83t-ccu.h>
103     #include <dt-bindings/reset/sun8i-a83t-ccu.h>
105     hdmi_phy: hdmi-phy@1ef0000 {
106         compatible = "allwinner,sun8i-a83t-hdmi-phy";
108         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
109         clock-names = "bus", "mod";
110         resets = <&ccu RST_BUS_HDMI0>;
111         reset-names = "phy";
112         #phy-cells = <0>;