Lines Matching +full:msi +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
10 - Liu Ying <victor.liu@nxp.com>
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
14 sitting together with the PHYs. It is not the same as the MSI bus coming
15 from i.MX8 System Controller Unit (SCU) which is used to control power,
16 clock and reset through the i.MX8 Distributed Slave System Controller (DSC).
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
19 that is, MSI clock and AHB clock, need to be enabled so that peripherals
25 like I2C controller, PWM controller, MIPI DSI controller and Control and
28 The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp
29 pixel link MSI bus controller and does not allow SCFW user to control it.
30 So, the controller's registers cannot be accessed by SCFW user. Hence,
31 the interrupts generated by the controller don't make any sense from SCFW
35 - $ref: simple-pm-bus.yaml#
37 # We need a select here so we don't match all nodes with 'simple-pm-bus'.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
44 - fsl,imx8qm-display-pixel-link-msi-bus
46 - compatible
51 - enum:
52 - fsl,imx8qxp-display-pixel-link-msi-bus
53 - fsl,imx8qm-display-pixel-link-msi-bus
54 - const: simple-pm-bus
64 - description: master gated clock from system
65 - description: AHB clock
67 clock-names:
69 - const: msi
70 - const: ahb
73 "^.*@[0-9a-f]+$":
78 - reg
81 - compatible
82 - reg
83 - clocks
84 - clock-names
85 - power-domains
90 - |
91 #include <dt-bindings/clock/imx8-lpcg.h>
92 #include <dt-bindings/firmware/imx/rsrc.h>
94 compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 interrupt-parent = <&dc0_irqsteer>;
103 clock-names = "msi", "ahb";
104 power-domains = <&pd IMX_SC_R_DC_0>;
107 compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
110 clock-names = "ipg";
113 compatible = "fsl,imx8qxp-pxl2dpi";
114 fsl,sc-resource = <IMX_SC_R_MIPI_0>;
115 power-domains = <&pd IMX_SC_R_MIPI_0>;
118 #address-cells = <1>;
119 #size-cells = <0>;
122 #address-cells = <1>;
123 #size-cells = <0>;
128 remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
133 remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
138 #address-cells = <1>;
139 #size-cells = <0>;
144 remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
149 remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "fsl,imx8qxp-ldb";
161 clock-names = "pixel", "bypass";
162 power-domains = <&pd IMX_SC_R_LVDS_0>;
165 #address-cells = <1>;
166 #size-cells = <0>;
169 phy-names = "lvds_phy";
175 remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
187 #address-cells = <1>;
188 #size-cells = <0>;
191 phy-names = "lvds_phy";
197 remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
210 clock-controller@56223004 {
211 compatible = "fsl,imx8qxp-lpcg";
213 #clock-cells = <1>;
215 clock-indices = <IMX_LPCG_CLK_4>;
216 clock-output-names = "mipi_lvds_0_di_mipi_lvds_regs_lpcg_ipg_clk";
217 power-domains = <&pd IMX_SC_R_MIPI_0>;
221 compatible = "fsl,imx8qxp-mipi-dphy";
224 clock-names = "phy_ref";
225 #phy-cells = <0>;
227 power-domains = <&pd IMX_SC_R_MIPI_0>;