1454 	IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);  in iwp_reset_rx_ring()
1628 	IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(ring->qid), 0);  in iwp_reset_tx_ring()
1977 	IWP_WRITE(sc, CSR_GP_CNTRL,  in iwp_mac_access_enter()
2006 	IWP_WRITE(sc, CSR_GP_CNTRL,  in iwp_mac_access_exit()
2026 	IWP_WRITE(sc, HBUS_TARG_MEM_WADDR, addr);  in iwp_mem_write()
2027 	IWP_WRITE(sc, HBUS_TARG_MEM_WDAT, data);  in iwp_mem_write()
2036 	IWP_WRITE(sc, HBUS_TARG_PRPH_RADDR, addr | (3 << 24));  in iwp_reg_read()
2046 	IWP_WRITE(sc, HBUS_TARG_PRPH_WADDR, addr | (3 << 24));  in iwp_reg_write()
2047 	IWP_WRITE(sc, HBUS_TARG_PRPH_WDAT, data);  in iwp_reg_write()
2752 	IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, index & (~7));  in iwp_rx_softintr()
2757 	IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);  in iwp_rx_softintr()
2793 	IWP_WRITE(sc, CSR_INT_MASK, 0);  in iwp_intr()
2798 	IWP_WRITE(sc, CSR_INT, r);  in iwp_intr()
2799 	IWP_WRITE(sc, CSR_FH_INT_STATUS, rfh);  in iwp_intr()
2846 	IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);  in iwp_intr()
3300 	IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->desc_cur);  in iwp_send()
3781 	IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);  in iwp_cmd()
4082 	IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);  in iwp_scan()
4266 	IWP_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_STOP_MASTER);  in iwp_stop_master()
4320 	IWP_WRITE(sc, CSR_INT, 0xffffffff);  in iwp_preinit()
4323 	IWP_WRITE(sc, CSR_GIO_CHICKEN_BITS,  in iwp_preinit()
4327 	IWP_WRITE(sc, CSR_GP_CNTRL, tmp | CSR_GP_CNTRL_REG_FLAG_INIT_DONE);  in iwp_preinit()
4357 		IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG,  in iwp_preinit()
4368 	IWP_WRITE(sc, CSR_INT_COALESCING, 512 / 32);  in iwp_preinit()
4388 	IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, tmp);  in iwp_preinit()
4405 		IWP_WRITE(sc, CSR_GP_DRIVER_REG,  in iwp_preinit()
4411 		IWP_WRITE(sc, CSR_GP_DRIVER_REG,  in iwp_preinit()
4429 		IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG,  in iwp_eep_sem_down()
4452 	IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG,  in iwp_eep_sem_up()
4486 		IWP_WRITE(sc, CSR_EEPROM_REG, addr<<1);  in iwp_eep_load()
4488 		IWP_WRITE(sc, CSR_EEPROM_REG, tmp & ~(0x2));  in iwp_eep_load()
4570 	IWP_WRITE(sc, CSR_RESET, 0);  in iwp_init()
4617 	IWP_WRITE(sc, CSR_RESET, 0);  in iwp_init()
4674 	IWP_WRITE(sc, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);  in iwp_stop()
4678 	IWP_WRITE(sc, CSR_INT_MASK, 0);  in iwp_stop()
4679 	IWP_WRITE(sc, CSR_INT, CSR_INI_SET_MASK);  in iwp_stop()
4680 	IWP_WRITE(sc, CSR_FH_INT_STATUS, 0xffffffff);  in iwp_stop()
4707 	IWP_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_SW_RESET);  in iwp_stop()
4879 	IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(IWP_FH_SRVC_CHNL),  in iwp_put_seg_fw()
4882 	IWP_WRITE(sc, IWP_FH_SRVC_CHNL_SRAM_ADDR_REG(IWP_FH_SRVC_CHNL), addr_d);  in iwp_put_seg_fw()
4884 	IWP_WRITE(sc, IWP_FH_TFDIB_CTRL0_REG(IWP_FH_SRVC_CHNL),  in iwp_put_seg_fw()
4887 	IWP_WRITE(sc, IWP_FH_TFDIB_CTRL1_REG(IWP_FH_SRVC_CHNL), len);  in iwp_put_seg_fw()
4889 	IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_BUF_STS_REG(IWP_FH_SRVC_CHNL),  in iwp_put_seg_fw()
4894 	IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(IWP_FH_SRVC_CHNL),  in iwp_put_seg_fw()
4951 		IWP_WRITE(sc, HBUS_TARG_WRPTR, 0 | (i << 8));  in iwp_alive_common()
4969 	IWP_WRITE(sc, HBUS_TARG_WRPTR, (IWP_CMD_QUEUE_NUM << 8));  in iwp_alive_common()
5160 	IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);  in iwp_init_common()
5162 	IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);  in iwp_init_common()
5163 	IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_BASE_REG,  in iwp_init_common()
5166 	IWP_WRITE(sc, FH_RSCSR_CHNL0_STTS_WPTR_REG,  in iwp_init_common()
5170 	IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG,  in iwp_init_common()
5177 	IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG,  in iwp_init_common()
5189 	IWP_WRITE(sc, IWP_FH_KW_MEM_ADDR_REG,  in iwp_init_common()
5193 		IWP_WRITE(sc, FH_MEM_CBBC_QUEUE(qid),  in iwp_init_common()
5195 		IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(qid),  in iwp_init_common()
5205 	IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);  in iwp_init_common()
5206 	IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR,  in iwp_init_common()
5212 	IWP_WRITE(sc, CSR_INT, 0xffffffff);  in iwp_init_common()
5217 	IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);  in iwp_init_common()
5219 	IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);  in iwp_init_common()
5220 	IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);  in iwp_init_common()