Lines Matching +full:0 +full:x4038
29 #define AR_CR 0x0008
30 #define AR_CR_RXE 0x00000004
31 #define AR_CR_RXD 0x00000020
32 #define AR_CR_SWI 0x00000040
34 #define AR_RXDP 0x000C
36 #define AR_CFG 0x0014
37 #define AR_CFG_SWTD 0x00000001
38 #define AR_CFG_SWTB 0x00000002
39 #define AR_CFG_SWRD 0x00000004
40 #define AR_CFG_SWRB 0x00000008
41 #define AR_CFG_SWRG 0x00000010
42 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020
43 #define AR_CFG_PHOK 0x00000100
44 #define AR_CFG_CLK_GATE_DIS 0x00000400
45 #define AR_CFG_EEBS 0x00000200
46 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000
49 #define AR_MIRT 0x0020
50 #define AR_MIRT_VAL 0x0000ffff
53 #define AR_IER 0x0024
54 #define AR_IER_ENABLE 0x00000001
55 #define AR_IER_DISABLE 0x00000000
57 #define AR_TIMT 0x0028
58 #define AR_TIMT_LAST 0x0000ffff
59 #define AR_TIMT_LAST_S 0
60 #define AR_TIMT_FIRST 0xffff0000
63 #define AR_RIMT 0x002C
64 #define AR_RIMT_LAST 0x0000ffff
65 #define AR_RIMT_LAST_S 0
66 #define AR_RIMT_FIRST 0xffff0000
69 #define AR_DMASIZE_4B 0x00000000
70 #define AR_DMASIZE_8B 0x00000001
71 #define AR_DMASIZE_16B 0x00000002
72 #define AR_DMASIZE_32B 0x00000003
73 #define AR_DMASIZE_64B 0x00000004
74 #define AR_DMASIZE_128B 0x00000005
75 #define AR_DMASIZE_256B 0x00000006
76 #define AR_DMASIZE_512B 0x00000007
78 #define AR_TXCFG 0x0030
79 #define AR_TXCFG_DMASZ_MASK 0x00000003
80 #define AR_TXCFG_DMASZ_4B 0
88 #define AR_FTRIG 0x000003F0
90 #define AR_FTRIG_IMMED 0x00000000
91 #define AR_FTRIG_64B 0x00000010
92 #define AR_FTRIG_128B 0x00000020
93 #define AR_FTRIG_192B 0x00000030
94 #define AR_FTRIG_256B 0x00000040
95 #define AR_FTRIG_512B 0x00000080
96 #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800
98 #define AR_RXCFG 0x0034
99 #define AR_RXCFG_CHIRP 0x00000008
100 #define AR_RXCFG_ZLFDMA 0x00000010
101 #define AR_RXCFG_DMASZ_MASK 0x00000007
102 #define AR_RXCFG_DMASZ_4B 0
111 #define AR_MIBC 0x0040
112 #define AR_MIBC_COW 0x00000001
113 #define AR_MIBC_FMC 0x00000002
114 #define AR_MIBC_CMC 0x00000004
115 #define AR_MIBC_MCS 0x00000008
117 #define AR_TOPS 0x0044
118 #define AR_TOPS_MASK 0x0000FFFF
120 #define AR_RXNPTO 0x0048
121 #define AR_RXNPTO_MASK 0x000003FF
123 #define AR_TXNPTO 0x004C
124 #define AR_TXNPTO_MASK 0x000003FF
125 #define AR_TXNPTO_QCU_MASK 0x000FFC00
127 #define AR_RPGTO 0x0050
128 #define AR_RPGTO_MASK 0x000003FF
130 #define AR_RPCNT 0x0054
131 #define AR_RPCNT_MASK 0x0000001F
133 #define AR_MACMISC 0x0058
134 #define AR_MACMISC_PCI_EXT_FORCE 0x00000010
135 #define AR_MACMISC_DMA_OBS 0x000001E0
137 #define AR_MACMISC_DMA_OBS_LINE_0 0
146 #define AR_MACMISC_MISC_OBS 0x00000E00
148 #define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000
150 #define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000
154 #define AR_GTXTO 0x0064
155 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF
156 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000
159 #define AR_GTTM 0x0068
160 #define AR_GTTM_USEC 0x00000001
161 #define AR_GTTM_IGNORE_IDLE 0x00000002
162 #define AR_GTTM_RESET_IDLE 0x00000004
163 #define AR_GTTM_CST_USEC 0x00000008
165 #define AR_CST 0x006C
166 #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF
167 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000
170 #define AR_SREV_VERSION_9100 0x014
177 #define AR_ISR 0x0080
178 #define AR_ISR_RXOK 0x00000001
179 #define AR_ISR_RXDESC 0x00000002
180 #define AR_ISR_RXERR 0x00000004
181 #define AR_ISR_RXNOPKT 0x00000008
182 #define AR_ISR_RXEOL 0x00000010
183 #define AR_ISR_RXORN 0x00000020
184 #define AR_ISR_TXOK 0x00000040
185 #define AR_ISR_TXDESC 0x00000080
186 #define AR_ISR_TXERR 0x00000100
187 #define AR_ISR_TXNOPKT 0x00000200
188 #define AR_ISR_TXEOL 0x00000400
189 #define AR_ISR_TXURN 0x00000800
190 #define AR_ISR_MIB 0x00001000
191 #define AR_ISR_SWI 0x00002000
192 #define AR_ISR_RXPHY 0x00004000
193 #define AR_ISR_RXKCM 0x00008000
194 #define AR_ISR_SWBA 0x00010000
195 #define AR_ISR_BRSSI 0x00020000
196 #define AR_ISR_BMISS 0x00040000
197 #define AR_ISR_BNR 0x00100000
198 #define AR_ISR_RXCHIRP 0x00200000
199 #define AR_ISR_BCNMISC 0x00800000
200 #define AR_ISR_TIM 0x00800000
201 #define AR_ISR_QCBROVF 0x02000000
202 #define AR_ISR_QCBRURN 0x04000000
203 #define AR_ISR_QTRIG 0x08000000
204 #define AR_ISR_GENTMR 0x10000000
206 #define AR_ISR_TXMINTR 0x00080000
207 #define AR_ISR_RXMINTR 0x01000000
208 #define AR_ISR_TXINTM 0x40000000
209 #define AR_ISR_RXINTM 0x80000000
211 #define AR_ISR_S0 0x0084
212 #define AR_ISR_S0_QCU_TXOK 0x000003FF
213 #define AR_ISR_S0_QCU_TXOK_S 0
214 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000
217 #define AR_ISR_S1 0x0088
218 #define AR_ISR_S1_QCU_TXERR 0x000003FF
219 #define AR_ISR_S1_QCU_TXERR_S 0
220 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000
223 #define AR_ISR_S2 0x008c
224 #define AR_ISR_S2_QCU_TXURN 0x000003FF
225 #define AR_ISR_S2_CST 0x00400000
226 #define AR_ISR_S2_GTT 0x00800000
227 #define AR_ISR_S2_TIM 0x01000000
228 #define AR_ISR_S2_CABEND 0x02000000
229 #define AR_ISR_S2_DTIMSYNC 0x04000000
230 #define AR_ISR_S2_BCNTO 0x08000000
231 #define AR_ISR_S2_CABTO 0x10000000
232 #define AR_ISR_S2_DTIM 0x20000000
233 #define AR_ISR_S2_TSFOOR 0x40000000
234 #define AR_ISR_S2_TBTT_TIME 0x80000000
236 #define AR_ISR_S3 0x0090
237 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF
238 #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000
240 #define AR_ISR_S4 0x0094
241 #define AR_ISR_S4_QCU_QTRIG 0x000003FF
242 #define AR_ISR_S4_RESV0 0xFFFFFC00
244 #define AR_ISR_S5 0x0098
245 #define AR_ISR_S5_TIMER_TRIG 0x000000FF
246 #define AR_ISR_S5_TIMER_THRESH 0x0007FE00
247 #define AR_ISR_S5_TIM_TIMER 0x00000010
248 #define AR_ISR_S5_DTIM_TIMER 0x00000020
249 #define AR_ISR_S5_S 0x00d8
250 #define AR_IMR_S5 0x00b8
251 #define AR_IMR_S5_TIM_TIMER 0x00000010
252 #define AR_IMR_S5_DTIM_TIMER 0x00000020
255 #define AR_IMR 0x00a0
256 #define AR_IMR_RXOK 0x00000001
257 #define AR_IMR_RXDESC 0x00000002
258 #define AR_IMR_RXERR 0x00000004
259 #define AR_IMR_RXNOPKT 0x00000008
260 #define AR_IMR_RXEOL 0x00000010
261 #define AR_IMR_RXORN 0x00000020
262 #define AR_IMR_TXOK 0x00000040
263 #define AR_IMR_TXDESC 0x00000080
264 #define AR_IMR_TXERR 0x00000100
265 #define AR_IMR_TXNOPKT 0x00000200
266 #define AR_IMR_TXEOL 0x00000400
267 #define AR_IMR_TXURN 0x00000800
268 #define AR_IMR_MIB 0x00001000
269 #define AR_IMR_SWI 0x00002000
270 #define AR_IMR_RXPHY 0x00004000
271 #define AR_IMR_RXKCM 0x00008000
272 #define AR_IMR_SWBA 0x00010000
273 #define AR_IMR_BRSSI 0x00020000
274 #define AR_IMR_BMISS 0x00040000
275 #define AR_IMR_BNR 0x00100000
276 #define AR_IMR_RXCHIRP 0x00200000
277 #define AR_IMR_BCNMISC 0x00800000
278 #define AR_IMR_TIM 0x00800000
279 #define AR_IMR_QCBROVF 0x02000000
280 #define AR_IMR_QCBRURN 0x04000000
281 #define AR_IMR_QTRIG 0x08000000
282 #define AR_IMR_GENTMR 0x10000000
284 #define AR_IMR_TXMINTR 0x00080000
285 #define AR_IMR_RXMINTR 0x01000000
286 #define AR_IMR_TXINTM 0x40000000
287 #define AR_IMR_RXINTM 0x80000000
289 #define AR_IMR_S0 0x00a4
290 #define AR_IMR_S0_QCU_TXOK 0x000003FF
291 #define AR_IMR_S0_QCU_TXOK_S 0
292 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000
295 #define AR_IMR_S1 0x00a8
296 #define AR_IMR_S1_QCU_TXERR 0x000003FF
297 #define AR_IMR_S1_QCU_TXERR_S 0
298 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000
301 #define AR_IMR_S2 0x00ac
302 #define AR_IMR_S2_QCU_TXURN 0x000003FF
303 #define AR_IMR_S2_QCU_TXURN_S 0
304 #define AR_IMR_S2_CST 0x00400000
305 #define AR_IMR_S2_GTT 0x00800000
306 #define AR_IMR_S2_TIM 0x01000000
307 #define AR_IMR_S2_CABEND 0x02000000
308 #define AR_IMR_S2_DTIMSYNC 0x04000000
309 #define AR_IMR_S2_BCNTO 0x08000000
310 #define AR_IMR_S2_CABTO 0x10000000
311 #define AR_IMR_S2_DTIM 0x20000000
312 #define AR_IMR_S2_TSFOOR 0x40000000
314 #define AR_IMR_S3 0x00b0
315 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF
316 #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000
319 #define AR_IMR_S4 0x00b4
320 #define AR_IMR_S4_QCU_QTRIG 0x000003FF
321 #define AR_IMR_S4_RESV0 0xFFFFFC00
323 #define AR_IMR_S5 0x00b8
324 #define AR_IMR_S5_TIMER_TRIG 0x000000FF
325 #define AR_IMR_S5_TIMER_THRESH 0x0000FF00
328 #define AR_ISR_RAC 0x00c0
329 #define AR_ISR_S0_S 0x00c4
330 #define AR_ISR_S0_QCU_TXOK 0x000003FF
331 #define AR_ISR_S0_QCU_TXOK_S 0
332 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000
335 #define AR_ISR_S1_S 0x00c8
336 #define AR_ISR_S1_QCU_TXERR 0x000003FF
337 #define AR_ISR_S1_QCU_TXERR_S 0
338 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000
341 #define AR_ISR_S2_S 0x00cc
342 #define AR_ISR_S3_S 0x00d0
343 #define AR_ISR_S4_S 0x00d4
344 #define AR_ISR_S5_S 0x00d8
345 #define AR_DMADBG_0 0x00e0
346 #define AR_DMADBG_1 0x00e4
347 #define AR_DMADBG_2 0x00e8
348 #define AR_DMADBG_3 0x00ec
349 #define AR_DMADBG_4 0x00f0
350 #define AR_DMADBG_5 0x00f4
351 #define AR_DMADBG_6 0x00f8
352 #define AR_DMADBG_7 0x00fc
355 #define AR_QCU_0 0x0001
356 #define AR_QCU_1 0x0002
357 #define AR_QCU_2 0x0004
358 #define AR_QCU_3 0x0008
359 #define AR_QCU_4 0x0010
360 #define AR_QCU_5 0x0020
361 #define AR_QCU_6 0x0040
362 #define AR_QCU_7 0x0080
363 #define AR_QCU_8 0x0100
364 #define AR_QCU_9 0x0200
366 #define AR_Q0_TXDP 0x0800
367 #define AR_Q1_TXDP 0x0804
368 #define AR_Q2_TXDP 0x0808
369 #define AR_Q3_TXDP 0x080c
370 #define AR_Q4_TXDP 0x0810
371 #define AR_Q5_TXDP 0x0814
372 #define AR_Q6_TXDP 0x0818
373 #define AR_Q7_TXDP 0x081c
374 #define AR_Q8_TXDP 0x0820
375 #define AR_Q9_TXDP 0x0824
378 #define AR_Q_TXE 0x0840
379 #define AR_Q_TXE_M 0x000003FF
381 #define AR_Q_TXD 0x0880
382 #define AR_Q_TXD_M 0x000003FF
384 #define AR_Q0_CBRCFG 0x08c0
385 #define AR_Q1_CBRCFG 0x08c4
386 #define AR_Q2_CBRCFG 0x08c8
387 #define AR_Q3_CBRCFG 0x08cc
388 #define AR_Q4_CBRCFG 0x08d0
389 #define AR_Q5_CBRCFG 0x08d4
390 #define AR_Q6_CBRCFG 0x08d8
391 #define AR_Q7_CBRCFG 0x08dc
392 #define AR_Q8_CBRCFG 0x08e0
393 #define AR_Q9_CBRCFG 0x08e4
395 #define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF
396 #define AR_Q_CBRCFG_INTERVAL_S 0
397 #define AR_Q_CBRCFG_OVF_THRESH 0xFF000000
400 #define AR_Q0_RDYTIMECFG 0x0900
401 #define AR_Q1_RDYTIMECFG 0x0904
402 #define AR_Q2_RDYTIMECFG 0x0908
403 #define AR_Q3_RDYTIMECFG 0x090c
404 #define AR_Q4_RDYTIMECFG 0x0910
405 #define AR_Q5_RDYTIMECFG 0x0914
406 #define AR_Q6_RDYTIMECFG 0x0918
407 #define AR_Q7_RDYTIMECFG 0x091c
408 #define AR_Q8_RDYTIMECFG 0x0920
409 #define AR_Q9_RDYTIMECFG 0x0924
411 #define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF
412 #define AR_Q_RDYTIMECFG_DURATION_S 0
413 #define AR_Q_RDYTIMECFG_EN 0x01000000
415 #define AR_Q_ONESHOTARM_SC 0x0940
416 #define AR_Q_ONESHOTARM_SC_M 0x000003FF
417 #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00
419 #define AR_Q_ONESHOTARM_CC 0x0980
420 #define AR_Q_ONESHOTARM_CC_M 0x000003FF
421 #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00
423 #define AR_Q0_MISC 0x09c0
424 #define AR_Q1_MISC 0x09c4
425 #define AR_Q2_MISC 0x09c8
426 #define AR_Q3_MISC 0x09cc
427 #define AR_Q4_MISC 0x09d0
428 #define AR_Q5_MISC 0x09d4
429 #define AR_Q6_MISC 0x09d8
430 #define AR_Q7_MISC 0x09dc
431 #define AR_Q8_MISC 0x09e0
432 #define AR_Q9_MISC 0x09e4
434 #define AR_Q_MISC_FSP 0x0000000F
435 #define AR_Q_MISC_FSP_ASAP 0
441 #define AR_Q_MISC_ONE_SHOT_EN 0x00000010
442 #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020
443 #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040
444 #define AR_Q_MISC_BEACON_USE 0x00000080
445 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100
446 #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200
447 #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400
448 #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800
449 #define AR_Q_MISC_RESV0 0xFFFFF000
451 #define AR_Q0_STS 0x0a00
452 #define AR_Q1_STS 0x0a04
453 #define AR_Q2_STS 0x0a08
454 #define AR_Q3_STS 0x0a0c
455 #define AR_Q4_STS 0x0a10
456 #define AR_Q5_STS 0x0a14
457 #define AR_Q6_STS 0x0a18
458 #define AR_Q7_STS 0x0a1c
459 #define AR_Q8_STS 0x0a20
460 #define AR_Q9_STS 0x0a24
462 #define AR_Q_STS_PEND_FR_CNT 0x00000003
463 #define AR_Q_STS_RESV0 0x000000FC
464 #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00
465 #define AR_Q_STS_RESV1 0xFFFF0000
467 #define AR_Q_RDYTIMESHDN 0x0a40
468 #define AR_Q_RDYTIMESHDN_M 0x000003FF
472 #define AR_DCU_0 0x0001
473 #define AR_DCU_1 0x0002
474 #define AR_DCU_2 0x0004
475 #define AR_DCU_3 0x0008
476 #define AR_DCU_4 0x0010
477 #define AR_DCU_5 0x0020
478 #define AR_DCU_6 0x0040
479 #define AR_DCU_7 0x0080
480 #define AR_DCU_8 0x0100
481 #define AR_DCU_9 0x0200
483 #define AR_D0_QCUMASK 0x1000
484 #define AR_D1_QCUMASK 0x1004
485 #define AR_D2_QCUMASK 0x1008
486 #define AR_D3_QCUMASK 0x100c
487 #define AR_D4_QCUMASK 0x1010
488 #define AR_D5_QCUMASK 0x1014
489 #define AR_D6_QCUMASK 0x1018
490 #define AR_D7_QCUMASK 0x101c
491 #define AR_D8_QCUMASK 0x1020
492 #define AR_D9_QCUMASK 0x1024
494 #define AR_D_QCUMASK 0x000003FF
495 #define AR_D_QCUMASK_RESV0 0xFFFFFC00
497 #define AR_D_TXBLK_CMD 0x1038
500 #define AR_D0_LCL_IFS 0x1040
501 #define AR_D1_LCL_IFS 0x1044
502 #define AR_D2_LCL_IFS 0x1048
503 #define AR_D3_LCL_IFS 0x104c
504 #define AR_D4_LCL_IFS 0x1050
505 #define AR_D5_LCL_IFS 0x1054
506 #define AR_D6_LCL_IFS 0x1058
507 #define AR_D7_LCL_IFS 0x105c
508 #define AR_D8_LCL_IFS 0x1060
509 #define AR_D9_LCL_IFS 0x1064
511 #define AR_D_LCL_IFS_CWMIN 0x000003FF
512 #define AR_D_LCL_IFS_CWMIN_S 0
513 #define AR_D_LCL_IFS_CWMAX 0x000FFC00
515 #define AR_D_LCL_IFS_AIFS 0x0FF00000
518 #define AR_D_LCL_IFS_RESV0 0xF0000000
520 #define AR_D0_RETRY_LIMIT 0x1080
521 #define AR_D1_RETRY_LIMIT 0x1084
522 #define AR_D2_RETRY_LIMIT 0x1088
523 #define AR_D3_RETRY_LIMIT 0x108c
524 #define AR_D4_RETRY_LIMIT 0x1090
525 #define AR_D5_RETRY_LIMIT 0x1094
526 #define AR_D6_RETRY_LIMIT 0x1098
527 #define AR_D7_RETRY_LIMIT 0x109c
528 #define AR_D8_RETRY_LIMIT 0x10a0
529 #define AR_D9_RETRY_LIMIT 0x10a4
531 #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F
532 #define AR_D_RETRY_LIMIT_FR_SH_S 0
533 #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00
535 #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000
537 #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000
539 #define AR_D0_CHNTIME 0x10c0
540 #define AR_D1_CHNTIME 0x10c4
541 #define AR_D2_CHNTIME 0x10c8
542 #define AR_D3_CHNTIME 0x10cc
543 #define AR_D4_CHNTIME 0x10d0
544 #define AR_D5_CHNTIME 0x10d4
545 #define AR_D6_CHNTIME 0x10d8
546 #define AR_D7_CHNTIME 0x10dc
547 #define AR_D8_CHNTIME 0x10e0
548 #define AR_D9_CHNTIME 0x10e4
550 #define AR_D_CHNTIME_DUR 0x000FFFFF
551 #define AR_D_CHNTIME_DUR_S 0
552 #define AR_D_CHNTIME_EN 0x00100000
553 #define AR_D_CHNTIME_RESV0 0xFFE00000
555 #define AR_D0_MISC 0x1100
556 #define AR_D1_MISC 0x1104
557 #define AR_D2_MISC 0x1108
558 #define AR_D3_MISC 0x110c
559 #define AR_D4_MISC 0x1110
560 #define AR_D5_MISC 0x1114
561 #define AR_D6_MISC 0x1118
562 #define AR_D7_MISC 0x111c
563 #define AR_D8_MISC 0x1120
564 #define AR_D9_MISC 0x1124
566 #define AR_D_MISC_BKOFF_THRESH 0x0000003F
567 #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040
568 #define AR_D_MISC_CW_RESET_EN 0x00000080
569 #define AR_D_MISC_FRAG_WAIT_EN 0x00000100
570 #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200
571 #define AR_D_MISC_CW_BKOFF_EN 0x00001000
572 #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000
574 #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0
576 #define AR_D_MISC_BEACON_USE 0x00010000
577 #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000
579 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0
582 #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000
583 #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000
584 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000
585 #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000
586 #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000
587 #define AR_D_MISC_RESV0 0xFF000000
589 #define AR_D_SEQNUM 0x1140
591 #define AR_D_GBL_IFS_SIFS 0x1030
592 #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF
593 #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF
595 #define AR_D_TXBLK_BASE 0x1038
596 #define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF
597 #define AR_D_TXBLK_WRITE_BITMASK_S 0
598 #define AR_D_TXBLK_WRITE_SLICE 0x000F0000
600 #define AR_D_TXBLK_WRITE_DCU 0x00F00000
602 #define AR_D_TXBLK_WRITE_COMMAND 0x0F000000
605 #define AR_D_GBL_IFS_SLOT 0x1070
606 #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF
607 #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000
609 #define AR_D_GBL_IFS_EIFS 0x10b0
610 #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF
611 #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000
613 #define AR_D_GBL_IFS_MISC 0x10f0
614 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007
615 #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008
616 #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00
617 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000
618 #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000
619 #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000
620 #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000
621 #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000
623 #define AR_D_FPCTL 0x1230
624 #define AR_D_FPCTL_DCU 0x0000000F
625 #define AR_D_FPCTL_DCU_S 0
626 #define AR_D_FPCTL_PREFETCH_EN 0x00000010
627 #define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0
630 #define AR_D_TXPSE 0x1270
631 #define AR_D_TXPSE_CTRL 0x000003FF
632 #define AR_D_TXPSE_RESV0 0x0000FC00
633 #define AR_D_TXPSE_STATUS 0x00010000
634 #define AR_D_TXPSE_RESV1 0xFFFE0000
636 #define AR_D_TXSLOTMASK 0x12f0
637 #define AR_D_TXSLOTMASK_NUM 0x0000000F
639 #define AR_CFG_LED 0x1f04
640 #define AR_CFG_SCLK_RATE_IND 0x00000003
641 #define AR_CFG_SCLK_RATE_IND_S 0
642 #define AR_CFG_SCLK_32MHZ 0x00000000
643 #define AR_CFG_SCLK_4MHZ 0x00000001
644 #define AR_CFG_SCLK_1MHZ 0x00000002
645 #define AR_CFG_SCLK_32KHZ 0x00000003
646 #define AR_CFG_LED_BLINK_SLOW 0x00000008
647 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070
648 #define AR_CFG_LED_MODE_SEL 0x00000380
650 #define AR_CFG_LED_POWER 0x00000280
652 #define AR_CFG_LED_NETWORK 0x00000300
654 #define AR_CFG_LED_MODE_PROP 0x0
655 #define AR_CFG_LED_MODE_RPROP 0x1
656 #define AR_CFG_LED_MODE_SPLIT 0x2
657 #define AR_CFG_LED_MODE_RAND 0x3
658 #define AR_CFG_LED_MODE_POWER_OFF 0x4
659 #define AR_CFG_LED_MODE_POWER_ON 0x5
660 #define AR_CFG_LED_MODE_NETWORK_OFF 0x4
661 #define AR_CFG_LED_MODE_NETWORK_ON 0x6
662 #define AR_CFG_LED_ASSOC_CTL 0x00000c00
664 #define AR_CFG_LED_ASSOC_NONE 0x0
665 #define AR_CFG_LED_ASSOC_ACTIVE 0x1
666 #define AR_CFG_LED_ASSOC_PENDING 0x2
668 #define AR_CFG_LED_BLINK_SLOW 0x00000008
671 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070
674 #define AR_MAC_SLEEP 0x1f00
675 #define AR_MAC_SLEEP_MAC_AWAKE 0x00000000
676 #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001
678 #define AR_RC 0x4000
679 #define AR_RC_AHB 0x00000001
680 #define AR_RC_APB 0x00000002
681 #define AR_RC_HOSTIF 0x00000100
683 #define AR_WA 0x4004
684 #define AR9285_WA_DEFAULT 0x004a05cb
685 #define AR9280_WA_DEFAULT 0x0040073f
686 #define AR_WA_DEFAULT 0x0000073f
688 #define AR_PM_STATE 0x4008
689 #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000
691 #define AR_HOST_TIMEOUT 0x4018
692 #define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF
693 #define AR_HOST_TIMEOUT_APB_CNTR_S 0
694 #define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000
697 #define AR_EEPROM 0x401c
698 #define AR_EEPROM_ABSENT 0x00000100
699 #define AR_EEPROM_CORRUPT 0x00000200
700 #define AR_EEPROM_PROT_MASK 0x03FFFC00
703 #define EEPROM_PROTECT_RP_0_31 0x0001
704 #define EEPROM_PROTECT_WP_0_31 0x0002
705 #define EEPROM_PROTECT_RP_32_63 0x0004
706 #define EEPROM_PROTECT_WP_32_63 0x0008
707 #define EEPROM_PROTECT_RP_64_127 0x0010
708 #define EEPROM_PROTECT_WP_64_127 0x0020
709 #define EEPROM_PROTECT_RP_128_191 0x0040
710 #define EEPROM_PROTECT_WP_128_191 0x0080
711 #define EEPROM_PROTECT_RP_192_255 0x0100
712 #define EEPROM_PROTECT_WP_192_255 0x0200
713 #define EEPROM_PROTECT_RP_256_511 0x0400
714 #define EEPROM_PROTECT_WP_256_511 0x0800
715 #define EEPROM_PROTECT_RP_512_1023 0x1000
716 #define EEPROM_PROTECT_WP_512_1023 0x2000
717 #define EEPROM_PROTECT_RP_1024_2047 0x4000
718 #define EEPROM_PROTECT_WP_1024_2047 0x8000
721 ((AR_SREV_9100(ah)) ? 0x0600 : 0x4020)
724 ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF)
725 #define AR_SREV_VERSION 0x000000F0
727 #define AR_SREV_REVISION 0x00000007
729 #define AR_SREV_ID2 0xFFFFFFFF
730 #define AR_SREV_VERSION2 0xFFFC0000
732 #define AR_SREV_TYPE2 0x0003F000
734 #define AR_SREV_TYPE2_CHAIN 0x00001000
735 #define AR_SREV_TYPE2_HOST_MODE 0x00002000
736 #define AR_SREV_REVISION2 0x00000F00
739 #define AR_SREV_VERSION_5416_PCI 0xD
740 #define AR_SREV_VERSION_5416_PCIE 0xC
741 #define AR_SREV_REVISION_5416_10 0
744 #define AR_SREV_VERSION_9160 0x40
745 #define AR_SREV_REVISION_9160_10 0
747 #define AR_SREV_VERSION_9280 0x80
748 #define AR_SREV_REVISION_9280_10 0
751 #define AR_SREV_VERSION_9285 0xC0
752 #define AR_SREV_REVISION_9285_10 0
796 #define AR_RADIO_SREV_MAJOR 0xf0
797 #define AR_RAD5133_SREV_MAJOR 0xc0
798 #define AR_RAD2133_SREV_MAJOR 0xd0
799 #define AR_RAD5122_SREV_MAJOR 0xe0
800 #define AR_RAD2122_SREV_MAJOR 0xf0
802 #define AR_AHB_MODE 0x4024
803 #define AR_AHB_EXACT_WR_EN 0x00000000
804 #define AR_AHB_BUF_WR_EN 0x00000001
805 #define AR_AHB_EXACT_RD_EN 0x00000000
806 #define AR_AHB_CACHELINE_RD_EN 0x00000002
807 #define AR_AHB_PREFETCH_RD_EN 0x00000004
808 #define AR_AHB_PAGE_SIZE_1K 0x00000000
809 #define AR_AHB_PAGE_SIZE_2K 0x00000008
810 #define AR_AHB_PAGE_SIZE_4K 0x00000010
812 #define AR_INTR_RTC_IRQ 0x00000001
813 #define AR_INTR_MAC_IRQ 0x00000002
814 #define AR_INTR_EEP_PROT_ACCESS 0x00000004
815 #define AR_INTR_MAC_AWAKE 0x00020000
816 #define AR_INTR_MAC_ASLEEP 0x00040000
817 #define AR_INTR_SPURIOUS 0xFFFFFFFF
820 #define AR_INTR_SYNC_CAUSE_CLR 0x4028
822 #define AR_INTR_SYNC_CAUSE 0x4028
824 #define AR_INTR_SYNC_ENABLE 0x402c
825 #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000
829 AR_INTR_SYNC_RTC_IRQ = 0x00000001,
830 AR_INTR_SYNC_MAC_IRQ = 0x00000002,
831 AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004,
832 AR_INTR_SYNC_APB_TIMEOUT = 0x00000008,
833 AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010,
834 AR_INTR_SYNC_HOST1_FATAL = 0x00000020,
835 AR_INTR_SYNC_HOST1_PERR = 0x00000040,
836 AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080,
837 AR_INTR_SYNC_RADM_CPL_EP = 0x00000100,
838 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200,
839 AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400,
840 AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800,
841 AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000,
842 AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000,
843 AR_INTR_SYNC_PM_ACCESS = 0x00004000,
844 AR_INTR_SYNC_MAC_AWAKE = 0x00008000,
845 AR_INTR_SYNC_MAC_ASLEEP = 0x00010000,
846 AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000,
847 AR_INTR_SYNC_ALL = 0x0003FFFF,
860 /* AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, */
865 #define AR_INTR_ASYNC_MASK 0x4030
866 #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000
869 #define AR_INTR_SYNC_MASK 0x4034
870 #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000
873 #define AR_INTR_ASYNC_CAUSE_CLR 0x4038
874 #define AR_INTR_ASYNC_CAUSE 0x4038
876 #define AR_INTR_ASYNC_ENABLE 0x403c
877 #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000
880 #define AR_PCIE_SERDES 0x4040
881 #define AR_PCIE_SERDES2 0x4044
882 #define AR_PCIE_PM_CTRL 0x4014
883 #define AR_PCIE_PM_CTRL_ENA 0x00080000
888 #define AR_GPIO_IN_OUT 0x4048
889 #define AR_GPIO_IN_VAL 0x0FFFC000
891 #define AR928X_GPIO_IN_VAL 0x000FFC00
894 #define AR_GPIO_OE_OUT 0x404c
895 #define AR_GPIO_OE_OUT_DRV 0x3
896 #define AR_GPIO_OE_OUT_DRV_NO 0x0
897 #define AR_GPIO_OE_OUT_DRV_LOW 0x1
898 #define AR_GPIO_OE_OUT_DRV_HI 0x2
899 #define AR_GPIO_OE_OUT_DRV_ALL 0x3
901 #define AR_GPIO_INTR_POL 0x4050
902 #define AR_GPIO_INTR_POL_VAL 0x00001FFF
903 #define AR_GPIO_INTR_POL_VAL_S 0
905 #define AR_GPIO_INPUT_EN_VAL 0x4054
906 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080
908 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000
910 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
911 #define AR_GPIO_JTAG_DISABLE 0x00020000
913 #define AR_GPIO_INPUT_MUX1 0x4058
915 #define AR_GPIO_INPUT_MUX2 0x405c
916 #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f
917 #define AR_GPIO_INPUT_MUX2_CLK25_S 0
918 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0
920 #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00
923 #define AR_GPIO_OUTPUT_MUX1 0x4060
924 #define AR_GPIO_OUTPUT_MUX2 0x4064
925 #define AR_GPIO_OUTPUT_MUX3 0x4068
927 #define AR_INPUT_STATE 0x406c
929 #define AR_EEPROM_STATUS_DATA 0x407c
930 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
931 #define AR_EEPROM_STATUS_DATA_VAL_S 0
932 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
933 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000
934 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
935 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
937 #define AR_OBS 0x4080
939 #define AR_PCIE_MSI 0x4094
940 #define AR_PCIE_MSI_ENABLE 0x00000001
943 #define AR_RTC_9160_PLL_DIV 0x000003ff
944 #define AR_RTC_9160_PLL_DIV_S 0
945 #define AR_RTC_9160_PLL_REFDIV 0x00003C00
947 #define AR_RTC_9160_PLL_CLKSEL 0x0000C000
950 #define AR_RTC_BASE 0x00020000
952 (AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000
953 #define AR_RTC_RC_M 0x00000003
954 #define AR_RTC_RC_MAC_WARM 0x00000001
955 #define AR_RTC_RC_MAC_COLD 0x00000002
956 #define AR_RTC_RC_COLD_RESET 0x00000004
957 #define AR_RTC_RC_WARM_RESET 0x00000008
960 (AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014
962 #define AR_RTC_PLL_DIV 0x0000001f
963 #define AR_RTC_PLL_DIV_S 0
964 #define AR_RTC_PLL_DIV2 0x00000020
965 #define AR_RTC_PLL_REFDIV_5 0x000000c0
966 #define AR_RTC_PLL_CLKSEL 0x00000300
972 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
973 #define AR_RTC_RESET_EN (0x00000001)
976 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044)
979 ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f)
981 #define AR_RTC_PM_STATUS_M 0x0000000f
983 #define AR_RTC_STATUS_SHUTDOWN 0x00000001
984 #define AR_RTC_STATUS_ON 0x00000002
985 #define AR_RTC_STATUS_SLEEP 0x00000004
986 #define AR_RTC_STATUS_WAKEUP 0x00000008
989 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)
990 #define AR_RTC_FORCE_DERIVED_CLK 0x2
993 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)
994 #define AR_RTC_FORCE_WAKE_EN 0x00000001
995 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002
999 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050)
1002 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054)
1005 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058)
1007 #define AR_SEQ_MASK 0x8060
1009 #define AR_AN_RF2G1_CH0 0x7810
1010 #define AR_AN_RF2G1_CH0_OB 0x03800000
1012 #define AR_AN_RF2G1_CH0_DB 0x1C000000
1015 #define AR_AN_RF5G1_CH0 0x7818
1016 #define AR_AN_RF5G1_CH0_OB5 0x00070000
1018 #define AR_AN_RF5G1_CH0_DB5 0x00380000
1021 #define AR_AN_RF2G1_CH1 0x7834
1022 #define AR_AN_RF2G1_CH1_OB 0x03800000
1024 #define AR_AN_RF2G1_CH1_DB 0x1C000000
1027 #define AR_AN_RF5G1_CH1 0x783C
1028 #define AR_AN_RF5G1_CH1_OB5 0x00070000
1030 #define AR_AN_RF5G1_CH1_DB5 0x00380000
1033 #define AR_AN_TOP2 0x7894
1034 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000
1036 #define AR_AN_TOP2_LOCALBIAS 0x00200000
1038 #define AR_AN_TOP2_PWDCLKIND 0x00400000
1041 #define AR_AN_SYNTH9 0x7868
1042 #define AR_AN_SYNTH9_REFDIVA 0xf8000000
1045 #define AR9285_AN_RF2G1 0x7820
1046 #define AR9285_AN_RF2G1_ENPACAL 0x00000800
1048 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000
1050 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000
1052 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000
1054 #define AR9285_AN_RF2G2 0x7824
1055 #define AR9285_AN_RF2G2_OFFCAL 0x00001000
1057 #define AR9285_AN_RF2G3 0x7828
1058 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
1060 #define AR9285_AN_RF2G3_OB_0 0x00E00000
1062 #define AR9285_AN_RF2G3_OB_1 0x001C0000
1064 #define AR9285_AN_RF2G3_OB_2 0x00038000
1066 #define AR9285_AN_RF2G3_OB_3 0x00007000
1068 #define AR9285_AN_RF2G3_OB_4 0x00000E00
1070 #define AR9285_AN_RF2G3_DB1_0 0x000001C0
1072 #define AR9285_AN_RF2G3_DB1_1 0x00000038
1074 #define AR9285_AN_RF2G3_DB1_2 0x00000007
1075 #define AR9285_AN_RF2G3_DB1_2_S 0
1076 #define AR9285_AN_RF2G4 0x782C
1077 #define AR9285_AN_RF2G4_DB1_3 0xE0000000
1079 #define AR9285_AN_RF2G4_DB1_4 0x1C000000
1081 #define AR9285_AN_RF2G4_DB2_0 0x03800000
1083 #define AR9285_AN_RF2G4_DB2_1 0x00700000
1085 #define AR9285_AN_RF2G4_DB2_2 0x000E0000
1087 #define AR9285_AN_RF2G4_DB2_3 0x0001C000
1089 #define AR9285_AN_RF2G4_DB2_4 0x00003800
1091 #define AR9285_AN_RF2G6 0x7834
1092 #define AR9285_AN_RF2G6_CCOMP 0x00007800
1094 #define AR9285_AN_RF2G6_OFFS 0x03f00000
1096 #define AR9285_AN_RF2G7 0x7838
1097 #define AR9285_AN_RF2G7_PWDDB 0x00000002
1099 #define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000
1101 #define AR9285_AN_RF2G8 0x783C
1102 #define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000
1104 #define AR9285_AN_RF2G9 0x7840
1105 #define AR9285_AN_RXTXBB1 0x7854
1106 #define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020
1108 #define AR9285_AN_RXTXBB1_PDV2I 0x00000080
1110 #define AR9285_AN_RXTXBB1_PDDACIF 0x00000100
1112 #define AR9285_AN_RXTXBB1_SPARE9 0x00000001
1113 #define AR9285_AN_RXTXBB1_SPARE9_S 0
1114 #define AR9285_AN_TOP2 0x7868
1115 #define AR9285_AN_TOP3 0x786c
1116 #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C
1118 #define AR9285_AN_TOP3_PWDDAC 0x00800000
1120 #define AR9285_AN_TOP4 0x7870
1121 #define AR9285_AN_TOP4_DEFAULT 0x10142c00
1122 #define AR_STA_ID0 0x8000
1123 #define AR_STA_ID1 0x8004
1124 #define AR_STA_ID1_SADH_MASK 0x0000FFFF
1125 #define AR_STA_ID1_STA_AP 0x00010000
1126 #define AR_STA_ID1_ADHOC 0x00020000
1127 #define AR_STA_ID1_PWR_SAV 0x00040000
1128 #define AR_STA_ID1_KSRCHDIS 0x00080000
1129 #define AR_STA_ID1_PCF 0x00100000
1130 #define AR_STA_ID1_USE_DEFANT 0x00200000
1131 #define AR_STA_ID1_DEFANT_UPDATE 0x00400000
1132 #define AR_STA_ID1_RTS_USE_DEF 0x00800000
1133 #define AR_STA_ID1_ACKCTS_6MB 0x01000000
1134 #define AR_STA_ID1_BASE_RATE_11B 0x02000000
1135 #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000
1136 #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000
1137 #define AR_STA_ID1_KSRCH_MODE 0x10000000
1138 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000
1139 #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000
1140 #define AR_STA_ID1_MCAST_KSRCH 0x80000000
1142 #define AR_BSS_ID0 0x8008
1143 #define AR_BSS_ID1 0x800C
1144 #define AR_BSS_ID1_U16 0x0000FFFF
1145 #define AR_BSS_ID1_AID 0x07FF0000
1148 #define AR_BCN_RSSI_AVE 0x8010
1149 #define AR_BCN_RSSI_AVE_MASK 0x00000FFF
1151 #define AR_TIME_OUT 0x8014
1152 #define AR_TIME_OUT_ACK 0x00003FFF
1153 #define AR_TIME_OUT_ACK_S 0
1154 #define AR_TIME_OUT_CTS 0x3FFF0000
1157 #define AR_RSSI_THR 0x8018
1158 #define AR_RSSI_THR_MASK 0x000000FF
1159 #define AR_RSSI_THR_BM_THR 0x0000FF00
1161 #define AR_RSSI_BCN_WEIGHT 0x1F000000
1163 #define AR_RSSI_BCN_RSSI_RST 0x20000000
1165 #define AR_USEC 0x801c
1166 #define AR_USEC_USEC 0x0000007F
1167 #define AR_USEC_TX_LAT 0x007FC000
1169 #define AR_USEC_RX_LAT 0x1F800000
1172 #define AR_RESET_TSF 0x8020
1173 #define AR_RESET_TSF_ONCE 0x01000000
1175 #define AR_MAX_CFP_DUR 0x8038
1176 #define AR_CFP_VAL 0x0000FFFF
1178 #define AR_RX_FILTER 0x803C
1179 #define AR_RX_FILTER_ALL 0x00000000
1180 #define AR_RX_UCAST 0x00000001
1181 #define AR_RX_MCAST 0x00000002
1182 #define AR_RX_BCAST 0x00000004
1183 #define AR_RX_CONTROL 0x00000008
1184 #define AR_RX_BEACON 0x00000010
1185 #define AR_RX_PROM 0x00000020
1186 #define AR_RX_PROBE_REQ 0x00000080
1187 #define AR_RX_MY_BEACON 0x00000200
1188 #define AR_RX_COMPR_BAR 0x00000400
1189 #define AR_RX_COMPR_BA 0x00000800
1190 #define AR_RX_UNCOM_BA_BAR 0x00001000
1192 #define AR_MCAST_FIL0 0x8040
1193 #define AR_MCAST_FIL1 0x8044
1195 #define AR_DIAG_SW 0x8048
1196 #define AR_DIAG_CACHE_ACK 0x00000001
1197 #define AR_DIAG_ACK_DIS 0x00000002
1198 #define AR_DIAG_CTS_DIS 0x00000004
1199 #define AR_DIAG_ENCRYPT_DIS 0x00000008
1200 #define AR_DIAG_DECRYPT_DIS 0x00000010
1201 #define AR_DIAG_RX_DIS 0x00000020
1202 #define AR_DIAG_LOOP_BACK 0x00000040
1203 #define AR_DIAG_CORR_FCS 0x00000080
1204 #define AR_DIAG_CHAN_INFO 0x00000100
1205 #define AR_DIAG_SCRAM_SEED 0x0001FE00
1207 #define AR_DIAG_FRAME_NV0 0x00020000
1208 #define AR_DIAG_OBS_PT_SEL1 0x000C0000
1210 #define AR_DIAG_FORCE_RX_CLEAR 0x00100000
1211 #define AR_DIAG_IGNORE_VIRT_CS 0x00200000
1212 #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000
1213 #define AR_DIAG_EIFS_CTRL_ENA 0x00800000
1214 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000
1215 #define AR_DIAG_RX_ABORT 0x02000000
1216 #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000
1217 #define AR_DIAG_OBS_PT_SEL2 0x08000000
1218 #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000
1219 #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000
1221 #define AR_TSF_L32 0x804c
1222 #define AR_TSF_U32 0x8050
1224 #define AR_TST_ADDAC 0x8054
1225 #define AR_DEF_ANTENNA 0x8058
1227 #define AR_AES_MUTE_MASK0 0x805c
1228 #define AR_AES_MUTE_MASK0_FC 0x0000FFFF
1229 #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000
1232 #define AR_AES_MUTE_MASK1 0x8060
1233 #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF
1235 #define AR_GATED_CLKS 0x8064
1236 #define AR_GATED_CLKS_TX 0x00000002
1237 #define AR_GATED_CLKS_RX 0x00000004
1238 #define AR_GATED_CLKS_REG 0x00000008
1240 #define AR_OBS_BUS_CTRL 0x8068
1241 #define AR_OBS_BUS_SEL_1 0x00040000
1242 #define AR_OBS_BUS_SEL_2 0x00080000
1243 #define AR_OBS_BUS_SEL_3 0x000C0000
1244 #define AR_OBS_BUS_SEL_4 0x08040000
1245 #define AR_OBS_BUS_SEL_5 0x08080000
1247 #define AR_OBS_BUS_1 0x806c
1248 #define AR_OBS_BUS_1_PCU 0x00000001
1249 #define AR_OBS_BUS_1_RX_END 0x00000002
1250 #define AR_OBS_BUS_1_RX_WEP 0x00000004
1251 #define AR_OBS_BUS_1_RX_BEACON 0x00000008
1252 #define AR_OBS_BUS_1_RX_FILTER 0x00000010
1253 #define AR_OBS_BUS_1_TX_HCF 0x00000020
1254 #define AR_OBS_BUS_1_QUIET_TIME 0x00000040
1255 #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080
1256 #define AR_OBS_BUS_1_TX_HOLD 0x00000100
1257 #define AR_OBS_BUS_1_TX_FRAME 0x00000200
1258 #define AR_OBS_BUS_1_RX_FRAME 0x00000400
1259 #define AR_OBS_BUS_1_RX_CLEAR 0x00000800
1260 #define AR_OBS_BUS_1_WEP_STATE 0x0003F000
1262 #define AR_OBS_BUS_1_RX_STATE 0x01F00000
1264 #define AR_OBS_BUS_1_TX_STATE 0x7E000000
1267 #define AR_LAST_TSTP 0x8080
1268 #define AR_NAV 0x8084
1269 #define AR_RTS_OK 0x8088
1270 #define AR_RTS_FAIL 0x808c
1271 #define AR_ACK_FAIL 0x8090
1272 #define AR_FCS_FAIL 0x8094
1273 #define AR_BEACON_CNT 0x8098
1275 #define AR_SLEEP1 0x80d4
1276 #define AR_SLEEP1_ASSUME_DTIM 0x00080000
1277 #define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000
1280 #define AR_SLEEP2 0x80d8
1281 #define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000
1284 #define AR_BSSMSKL 0x80e0
1285 #define AR_BSSMSKU 0x80e4
1287 #define AR_TPC 0x80e8
1288 #define AR_TPC_ACK 0x0000003f
1289 #define AR_TPC_ACK_S 0x00
1290 #define AR_TPC_CTS 0x00003f00
1291 #define AR_TPC_CTS_S 0x08
1292 #define AR_TPC_CHIRP 0x003f0000
1293 #define AR_TPC_CHIRP_S 0x16
1295 #define AR_TFCNT 0x80ec
1296 #define AR_RFCNT 0x80f0
1297 #define AR_RCCNT 0x80f4
1298 #define AR_CCCNT 0x80f8
1300 #define AR_QUIET1 0x80fc
1301 #define AR_QUIET1_NEXT_QUIET_S 0
1302 #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff
1303 #define AR_QUIET1_QUIET_ENABLE 0x00010000
1304 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000
1305 #define AR_QUIET2 0x8100
1306 #define AR_QUIET2_QUIET_PERIOD_S 0
1307 #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff
1309 #define AR_QUIET2_QUIET_DUR 0xffff0000
1311 #define AR_TSF_PARM 0x8104
1312 #define AR_TSF_INCREMENT_M 0x000000ff
1313 #define AR_TSF_INCREMENT_S 0x00
1315 #define AR_QOS_NO_ACK 0x8108
1316 #define AR_QOS_NO_ACK_TWO_BIT 0x0000000f
1317 #define AR_QOS_NO_ACK_TWO_BIT_S 0
1318 #define AR_QOS_NO_ACK_BIT_OFF 0x00000070
1320 #define AR_QOS_NO_ACK_BYTE_OFF 0x00000180
1323 #define AR_PHY_ERR 0x810c
1325 #define AR_PHY_ERR_DCHIRP 0x00000008
1326 #define AR_PHY_ERR_RADAR 0x00000020
1327 #define AR_PHY_ERR_OFDM_TIMING 0x00020000
1328 #define AR_PHY_ERR_CCK_TIMING 0x02000000
1330 #define AR_RXFIFO_CFG 0x8114
1333 #define AR_MIC_QOS_CONTROL 0x8118
1334 #define AR_MIC_QOS_SELECT 0x811c
1336 #define AR_PCU_MISC 0x8120
1337 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001
1338 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004
1339 #define AR_PCU_TX_ADD_TSF 0x00000008
1340 #define AR_PCU_CCK_SIFS_MODE 0x00000010
1341 #define AR_PCU_RX_ANT_UPDT 0x00000800
1342 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000
1343 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000
1344 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000
1345 #define AR_PCU_FORCE_QUIET_COLL 0x00040000
1346 #define AR_PCU_TBTT_PROTECT 0x00200000
1347 #define AR_PCU_CLEAR_VMF 0x01000000
1348 #define AR_PCU_CLEAR_BA_VALID 0x04000000
1351 #define AR_FILT_OFDM 0x8124
1352 #define AR_FILT_OFDM_COUNT 0x00FFFFFF
1354 #define AR_FILT_CCK 0x8128
1355 #define AR_FILT_CCK_COUNT 0x00FFFFFF
1357 #define AR_PHY_ERR_1 0x812c
1358 #define AR_PHY_ERR_1_COUNT 0x00FFFFFF
1359 #define AR_PHY_ERR_MASK_1 0x8130
1361 #define AR_PHY_ERR_2 0x8134
1362 #define AR_PHY_ERR_2_COUNT 0x00FFFFFF
1363 #define AR_PHY_ERR_MASK_2 0x8138
1368 #define AR_TSFOOR_THRESHOLD 0x813c
1369 #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF
1373 #define AR_PHY_ERR_3 0x8168
1374 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF
1375 #define AR_PHY_ERR_MASK_3 0x816c
1377 #define AR_TXSIFS 0x81d0
1378 #define AR_TXSIFS_TIME 0x000000FF
1379 #define AR_TXSIFS_TX_LATENCY 0x00000F00
1381 #define AR_TXSIFS_ACK_SHIFT 0x00007000
1384 #define AR_TXOP_X 0x81ec
1385 #define AR_TXOP_X_VAL 0x000000FF
1388 #define AR_TXOP_0_3 0x81f0
1389 #define AR_TXOP_4_7 0x81f4
1390 #define AR_TXOP_8_11 0x81f8
1391 #define AR_TXOP_12_15 0x81fc
1394 #define AR_NEXT_TBTT_TIMER 0x8200
1395 #define AR_NEXT_DMA_BEACON_ALERT 0x8204
1396 #define AR_NEXT_SWBA 0x8208
1397 #define AR_NEXT_CFP 0x8208
1398 #define AR_NEXT_HCF 0x820C
1399 #define AR_NEXT_TIM 0x8210
1400 #define AR_NEXT_DTIM 0x8214
1401 #define AR_NEXT_QUIET_TIMER 0x8218
1402 #define AR_NEXT_NDP_TIMER 0x821C
1404 #define AR_BEACON_PERIOD 0x8220
1405 #define AR_DMA_BEACON_PERIOD 0x8224
1406 #define AR_SWBA_PERIOD 0x8228
1407 #define AR_HCF_PERIOD 0x822C
1408 #define AR_TIM_PERIOD 0x8230
1409 #define AR_DTIM_PERIOD 0x8234
1410 #define AR_QUIET_PERIOD 0x8238
1411 #define AR_NDP_PERIOD 0x823C
1413 #define AR_TIMER_MODE 0x8240
1414 #define AR_TBTT_TIMER_EN 0x00000001
1415 #define AR_DBA_TIMER_EN 0x00000002
1416 #define AR_SWBA_TIMER_EN 0x00000004
1417 #define AR_HCF_TIMER_EN 0x00000008
1418 #define AR_TIM_TIMER_EN 0x00000010
1419 #define AR_DTIM_TIMER_EN 0x00000020
1420 #define AR_QUIET_TIMER_EN 0x00000040
1421 #define AR_NDP_TIMER_EN 0x00000080
1422 #define AR_TIMER_OVERFLOW_INDEX 0x00000700
1424 #define AR_TIMER_THRESH 0xFFFFF000
1427 #define AR_SLP32_MODE 0x8244
1428 #define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF
1429 #define AR_SLP32_ENA 0x00100000
1430 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000
1432 #define AR_SLP32_WAKE 0x8248
1433 #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF
1435 #define AR_SLP32_INC 0x824c
1436 #define AR_SLP32_TST_INC 0x000FFFFF
1438 #define AR_SLP_CNT 0x8250
1439 #define AR_SLP_CYCLE_CNT 0x8254
1441 #define AR_SLP_MIB_CTRL 0x8258
1442 #define AR_SLP_MIB_CLEAR 0x00000001
1443 #define AR_SLP_MIB_PENDING 0x00000002
1445 #define AR_2040_MODE 0x8318
1446 #define AR_2040_JOINED_RX_CLEAR 0x00000001
1449 #define AR_EXTRCCNT 0x8328
1451 #define AR_SELFGEN_MASK 0x832c
1453 #define AR_PCU_TXBUF_CTRL 0x8340
1454 #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF
1455 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700
1456 #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380
1458 #define AR_KEYTABLE_0 0x8800
1462 #define AR_KEY_TYPE 0x00000007
1463 #define AR_KEYTABLE_TYPE_40 0x00000000
1464 #define AR_KEYTABLE_TYPE_104 0x00000001
1465 #define AR_KEYTABLE_TYPE_128 0x00000003
1466 #define AR_KEYTABLE_TYPE_TKIP 0x00000004
1467 #define AR_KEYTABLE_TYPE_AES 0x00000005
1468 #define AR_KEYTABLE_TYPE_CCM 0x00000006
1469 #define AR_KEYTABLE_TYPE_CLR 0x00000007
1470 #define AR_KEYTABLE_ANT 0x00000008
1471 #define AR_KEYTABLE_VALID 0x00008000
1472 #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0)