255 u32 BASE;  variable
344 	data = inl(BASE + TLAN_HOST_CMD);  in TLan_ResetAdapter()
346 	outl(data, BASE + TLAN_HOST_CMD);  in TLan_ResetAdapter()
352 	data = inl(BASE + TLAN_HOST_CMD);  in TLan_ResetAdapter()
354 	outl(data, BASE + TLAN_HOST_CMD);  in TLan_ResetAdapter()
358 		TLan_DioWrite32(BASE, (u16) i, 0);  in TLan_ResetAdapter()
365 	TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);  in TLan_ResetAdapter()
369 	outl(TLAN_HC_LD_TMR | 0x3f, BASE + TLAN_HOST_CMD);  in TLan_ResetAdapter()
370 	outl(TLAN_HC_LD_THR | 0x0, BASE + TLAN_HOST_CMD);  in TLan_ResetAdapter()
374 	outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);  in TLan_ResetAdapter()
375 	addr = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;  in TLan_ResetAdapter()
382 		TLan_DioWrite8(BASE, TLAN_INT_DIS, data8);  in TLan_ResetAdapter()
390 			TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x0a);  in TLan_ResetAdapter()
392 			TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x00);  in TLan_ResetAdapter()
395 			TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x08);  in TLan_ResetAdapter()
402 	TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);  in TLan_ResetAdapter()
431 	TLan_DioWrite8(BASE, TLAN_NET_CMD, data);  in TLan_FinishReset()
436 	TLan_DioWrite8(BASE, TLAN_NET_MASK, data);  in TLan_FinishReset()
437 	TLan_DioWrite16(BASE, TLAN_MAX_RX, ((1536) + 7) & ~7);  in TLan_FinishReset()
478 			TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);  in TLan_FinishReset()
489 			TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);  in TLan_FinishReset()
497 		sio = TLan_DioRead8(BASE, TLAN_NET_SIO);  in TLan_FinishReset()
499 		TLan_DioWrite8(BASE, TLAN_NET_SIO, sio);  in TLan_FinishReset()
505 		outb((TLAN_HC_INT_ON >> 8), BASE + TLAN_HOST_CMD + 1);  in TLan_FinishReset()
511 		outl(virt_to_bus(&rx_ring), BASE + TLAN_CH_PARM);  in TLan_FinishReset()
512 		outl(TLAN_HC_GO | TLAN_HC_RT, BASE + TLAN_HOST_CMD);  in TLan_FinishReset()
540 	u16 host_int = inw(BASE + TLAN_HOST_INT);  in tlan_poll()
545 	outw(host_int, BASE + TLAN_HOST_INT);  in tlan_poll()
577 			outl(host_cmd, BASE + TLAN_HOST_CMD);  in tlan_poll()
581 		outl(host_cmd, BASE + TLAN_HOST_CMD);  in tlan_poll()
583 		printf("AC: 0x%hX\n", inw(BASE + TLAN_CH_PARM));   in tlan_poll()
584 		host_int = inw(BASE + TLAN_HOST_INT);  in tlan_poll()
626 	u16 host_int = inw(BASE + TLAN_HOST_INT);  in tlan_transmit()
692 	host_int = inw(BASE + TLAN_HOST_INT);  in tlan_transmit()
698 		outl(virt_to_le32desc(tail_list), BASE + TLAN_CH_PARM);  in tlan_transmit()
699 		outl(TLAN_HC_GO, BASE + TLAN_HOST_CMD);  in tlan_transmit()
719 	host_int = inw(BASE + TLAN_HOST_INT);  in tlan_transmit()
743 			outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);  in tlan_transmit()
751 		outl(host_cmd, BASE + TLAN_HOST_CMD);  in tlan_transmit()
758 			outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);  in tlan_transmit()
764 		outl(host_cmd, BASE + TLAN_HOST_CMD);  in tlan_transmit()
793 	outl(TLAN_HC_AD_RST, BASE + TLAN_HOST_CMD);  in tlan_disable()
816 	tmp = TLan_DioRead8(BASE, TLAN_NET_CMD);  in TLan_SetMulticastList()
817 	TLan_DioWrite8(BASE, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF);  in TLan_SetMulticastList()
822 	TLan_DioWrite32(BASE, TLAN_HASH_1, 0xFFFFFFFF);  in TLan_SetMulticastList()
823 	TLan_DioWrite32(BASE, TLAN_HASH_2, 0xFFFFFFFF);  in TLan_SetMulticastList()
851 	BASE = pci->ioaddr;
883 		err |= TLan_EeReadByte(BASE,
893 	priv->tlanRev = TLan_DioRead8(BASE, TLAN_DEF_REVISION);
904 	data = inl(BASE + TLAN_HOST_CMD);
906 	outw(data, BASE + TLAN_HOST_CMD);
1194 	outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1195 	sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1197 	TLan_MiiSync(BASE);
1203 	TLan_MiiSendData(BASE, 0x1, 2);	/* Start ( 01b ) */
1204 	TLan_MiiSendData(BASE, 0x2, 2);	/* Read  ( 10b ) */
1205 	TLan_MiiSendData(BASE, phy, 5);	/* Device #      */
1206 	TLan_MiiSendData(BASE, reg, 5);	/* Register #    */
1350 	outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1351 	sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1353 	TLan_MiiSync(BASE);
1359 	TLan_MiiSendData(BASE, 0x1, 2);	/* Start ( 01b ) */
1360 	TLan_MiiSendData(BASE, 0x1, 2);	/* Write ( 01b ) */
1361 	TLan_MiiSendData(BASE, phy, 5);	/* Device #      */
1362 	TLan_MiiSendData(BASE, reg, 5);	/* Register #    */
1364 	TLan_MiiSendData(BASE, 0x2, 2);	/* Send ACK */
1365 	TLan_MiiSendData(BASE, val, 16);	/* Send Data */
1405 			TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i,
1409 			TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i, 0);
1484 	TLan_MiiSync(BASE);
1490 		TLan_MiiSync(BASE);
1510 	TLan_MiiSync(BASE);
1513 	TLan_MiiSync(BASE);
1532 	TLan_MiiSync(BASE);
1611 		TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1699 		TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);