Lines Matching +full:mode +full:- +full:capable

3 /*-
48 #define	MII_BMCR	0x00	/* Basic mode control register (rw) */
56 #define	BMCR_FDX	0x0100	/* Set duplex mode */
66 #define	MII_BMSR	0x01	/* Basic mode status register (ro) */
67 #define	BMSR_100T4	0x8000	/* 100 base T4 capable */
68 #define	BMSR_100TXFDX	0x4000	/* 100 base Tx full duplex capable */
69 #define	BMSR_100TXHDX	0x2000	/* 100 base Tx half duplex capable */
70 #define	BMSR_10TFDX	0x1000	/* 10 base T full duplex capable */
71 #define	BMSR_10THDX	0x0800	/* 10 base T half duplex capable */
72 #define	BMSR_100T2FDX	0x0400	/* 100 base T2 full duplex capable */
73 #define	BMSR_100T2HDX	0x0200	/* 100 base T2 half duplex capable */
78 #define	BMSR_ANEG	0x0008	/* Autonegotiation capable */
88  * states that all 1000 Mb/s capable PHYs will set this bit to 1.
126 #define	ANAR_X_FD	0x0020	/* local device supports 1000BASE-X FD */
127 #define	ANAR_X_HD	0x0040	/* local device supports 1000BASE-X HD */
151 #define	ANLPAR_X_FD	0x0020	/* local device supports 1000BASE-X FD */
152 #define	ANLPAR_X_HD	0x0040	/* local device supports 1000BASE-X HD */
162 #define ANER_LPNP	0x0008	/* link parter next page-able */
163 #define ANER_NP		0x0004	/* next page-able */
165 #define ANER_LPAN	0x0001	/* link parter autoneg-able */
174 #define	MII_100T2CR	0x09	/* 100base-T2 control register */
183 #define	MII_100T2SR	0x0a	/* 100base-T2 status register */
188 #define	GTSR_LP_1000TFDX 0x0800	/* link partner 1000baseT FDX capable */
189 #define	GTSR_LP_1000THDX 0x0400	/* link partner 1000baseT HDX capable */
190 #define	GTSR_LP_ASM_DIR	0x0200	/* link partner asym. pause dir. capable */
198 #define	PSECR_FOPOWTST	0x0002	/* Force Power Test Mode */
229 #define	EXTSR_1000XFDX	0x8000	/* 1000X full-duplex capable */
230 #define	EXTSR_1000XHDX	0x4000	/* 1000X half-duplex capable */
231 #define	EXTSR_1000TFDX	0x2000	/* 1000T full-duplex capable */
232 #define	EXTSR_1000THDX	0x1000	/* 1000T half-duplex capable */