Lines Matching full:dispatch

145 .B \-dispatch=<width>
146 Specify a different dispatch width for the processor. The dispatch width
148 zero, then the default dispatch width is used.
214 .B \-dispatch\-stats
215 Enable extra dispatch statistics. This view collects and analyzes instruction
216 dispatch events, as well as static/dynamic dispatch stall events. This view
250 dispatch logic, the hardware schedulers, the register file(s), and the retire
570 Dispatch Width:    2
643 dispatch rate, and the availability of hardware resources.
650 opcodes by the total number of cycles. A delta between Dispatch Width and this
656 Field \fIuOps Per Cycle\fP is bounded from above by the dispatch width. That is
657 because the dispatch width limits the maximum size of a dispatch group. Both IPC
661 cycle.  A delta between Dispatch Width and the theoretical maximum uOps per
670 the Dispatch Width (2.00), and the theoretical maximum uOp throughput (1.50) is
862 least 1cy between the dispatch event and the issue event.
880 dynamic dispatch stalls.
936 counters for the dispatch logic, the reorder buffer, the retire control unit,
947 Dynamic Dispatch Stall Cycles:
953 GROUP   \- Static restrictions on the dispatch group: 0
956 Dispatch Logic \- number of cycles where we saw N micro opcodes dispatched:
1010 If we look at the \fIDynamic Dispatch Stall Cycles\fP table, we see the counter for
1011 SCHEDQ reports 272 cycles.  This counter is incremented every time the dispatch
1012 logic is unable to dispatch a full group because the scheduler\(aqs queue is full.
1014 Looking at the \fIDispatch Logic\fP table, we see that the pipeline was only able to
1015 dispatch two micro opcodes 51.5% of the time.  The dispatch group was limited to
1017 dispatch statistics are displayed by either using the command option
1018 \fB\-all\-stats\fP or \fB\-dispatch\-stats\fP\&.
1081 Dispatch (Instruction is dispatched to the schedulers).
1098 .SS Instruction Dispatch
1100 During the dispatch stage, instructions are picked in program order from a
1104 The size of a dispatch group depends on the availability of the simulated
1105 hardware resources.  The processor dispatch width defaults to the value
1111 The size of the dispatch group is smaller than processor\(aqs dispatch width.
1126 dispatch stalls caused by the lack of physical registers.
1278 bypasses Dispatch, Scheduler and Load/Store unit. Instructions are issued as