Lines Matching +full:feedback +full:- +full:pin
1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
51 #define CR0_NW 0x20000000 /* Not Write-through */
63 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
75 #define CR4_LA57 0x00001000 /* Enable 5-level paging */
77 (Intel-specific) */
82 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution
84 #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access
87 #define CR4_CET 0x00800000 /* Control-flow Enforcement
92 #define CR4_LAM_SUP 0x10000000 /* Linear-Address Masking for
101 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
211 #define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */
220 #define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */
321 * MWAIT cpu power states. Lower 4 bits are sub-states.
382 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
391 * Sub-leaf > 1 ecx info
587 * Model-specific registers for the i386 family
828 * Intel Hardware Feedback Interface / Thread Director MSRs
863 * document 336996-001 Speculative Execution Side Channel Mitigations.
865 * AMD uses the same MSRs and bit definitions, as described in 111006-B
938 #define MTRR_N64K 8 /* numbers of fixed-size entries */
957 non-cacheable */
958 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
959 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
960 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
961 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
982 #define CCR2_WPR1 0x10 /* Write-protect region 1 */
983 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
1006 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
1106 * The following four 3-byte registers control the non-cacheable regions.
1109 * NCRx+0: A31-A24 of starting address
1110 * NCRx+1: A23-A16 of starting address
1111 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
1113 * The non-cacheable region's starting address must be aligned to the
1142 * ARRx + 0: A31-A24 of start address
1143 * ARRx + 1: A23-A16 of start address
1144 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
1185 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
1190 #define RCR_WT 0x10 /* Write-through. */
1191 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
1193 /* AMD Write Allocate Top-Of-Memory and Control Register */
1194 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
1196 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
1228 #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
1229 #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
1230 #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
1231 #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
1261 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
1275 /* VIA ACE xcrypt-* instruction context control options */