Lines Matching +full:0 +full:x00000400
38 #define CR0_PE 0x00000001 /* Protected mode Enable */
39 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
40 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
41 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
42 #define CR0_PG 0x80000000 /* PaGing enable */
47 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
48 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
50 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
51 #define CR0_NW 0x20000000 /* Not Write-through */
52 #define CR0_CD 0x40000000 /* Cache Disable */
54 #define CR3_PCID_MASK 0x0000000000000fff
55 #define CR3_LAM_U57 0x2000000000000000
56 #define CR3_LAM_U48 0x4000000000000000
57 #define CR3_PCID_SAVE 0x8000000000000000
62 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
63 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
64 #define CR4_TSD 0x00000004 /* Time stamp disable */
65 #define CR4_DE 0x00000008 /* Debugging extensions */
66 #define CR4_PSE 0x00000010 /* Page size extensions */
67 #define CR4_PAE 0x00000020 /* Physical address extension */
68 #define CR4_MCE 0x00000040 /* Machine check enable */
69 #define CR4_PGE 0x00000080 /* Page global enable */
70 #define CR4_PCE 0x00000100 /* Performance monitoring counter
72 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
73 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
74 #define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */
75 #define CR4_LA57 0x00001000 /* Enable 5-level paging */
76 #define CR4_VMXE 0x00002000 /* enable VMX operation
78 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE access
80 #define CR4_PCIDE 0x00020000 /* Enable Context ID */
81 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
82 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution
84 #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access
86 #define CR4_PKE 0x00400000 /* Protection Keys Enable */
87 #define CR4_CET 0x00800000 /* Control-flow Enforcement
89 #define CR4_PKS 0x01000000 /* Protection Keys for Supervisor */
90 #define CR4_UINTR 0x02000000 /* User Interrupts Enable */
91 #define CR4_LASS 0x08000000 /* Linear Address Space Separation */
92 #define CR4_LAM_SUP 0x10000000 /* Linear-Address Masking for
98 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
99 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
100 #define EFER_LMA 0x000000400 /* Long mode active (R) */
101 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
102 #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved
104 #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */
105 #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */
106 #define EFER_TCE 0x000008000 /* Translation Cache Extension */
107 #define EFER_MCOMMIT 0x000020000 /* Enable MCOMMIT (AMD) */
108 #define EFER_INTWB 0x000040000 /* Interruptible WBINVD */
109 #define EFER_UAIE 0x000100000 /* Upper Address Ignore */
110 #define EFER_AIBRSE 0x000200000 /* Automatic IBRS */
115 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */
117 #define XFEATURE_ENABLED_X87 0x00000001
118 #define XFEATURE_ENABLED_SSE 0x00000002
119 #define XFEATURE_ENABLED_YMM_HI128 0x00000004
121 #define XFEATURE_ENABLED_BNDREGS 0x00000008
122 #define XFEATURE_ENABLED_BNDCSR 0x00000010
123 #define XFEATURE_ENABLED_OPMASK 0x00000020
124 #define XFEATURE_ENABLED_ZMM_HI256 0x00000040
125 #define XFEATURE_ENABLED_HI16_ZMM 0x00000080
126 #define XFEATURE_ENABLED_PKRU 0x00000200
127 #define XFEATURE_ENABLED_TILECONFIG 0x00020000
128 #define XFEATURE_ENABLED_TILEDATA 0x00040000
141 #define CPUID_FPU 0x00000001
142 #define CPUID_VME 0x00000002
143 #define CPUID_DE 0x00000004
144 #define CPUID_PSE 0x00000008
145 #define CPUID_TSC 0x00000010
146 #define CPUID_MSR 0x00000020
147 #define CPUID_PAE 0x00000040
148 #define CPUID_MCE 0x00000080
149 #define CPUID_CX8 0x00000100
150 #define CPUID_APIC 0x00000200
151 #define CPUID_B10 0x00000400
152 #define CPUID_SEP 0x00000800
153 #define CPUID_MTRR 0x00001000
154 #define CPUID_PGE 0x00002000
155 #define CPUID_MCA 0x00004000
156 #define CPUID_CMOV 0x00008000
157 #define CPUID_PAT 0x00010000
158 #define CPUID_PSE36 0x00020000
159 #define CPUID_PSN 0x00040000
160 #define CPUID_CLFSH 0x00080000
161 #define CPUID_B20 0x00100000
162 #define CPUID_DS 0x00200000
163 #define CPUID_ACPI 0x00400000
164 #define CPUID_MMX 0x00800000
165 #define CPUID_FXSR 0x01000000
166 #define CPUID_SSE 0x02000000
167 #define CPUID_XMM 0x02000000
168 #define CPUID_SSE2 0x04000000
169 #define CPUID_SS 0x08000000
170 #define CPUID_HTT 0x10000000
171 #define CPUID_TM 0x20000000
172 #define CPUID_IA64 0x40000000
173 #define CPUID_PBE 0x80000000
175 #define CPUID2_SSE3 0x00000001
176 #define CPUID2_PCLMULQDQ 0x00000002
177 #define CPUID2_DTES64 0x00000004
178 #define CPUID2_MON 0x00000008
179 #define CPUID2_DS_CPL 0x00000010
180 #define CPUID2_VMX 0x00000020
181 #define CPUID2_SMX 0x00000040
182 #define CPUID2_EST 0x00000080
183 #define CPUID2_TM2 0x00000100
184 #define CPUID2_SSSE3 0x00000200
185 #define CPUID2_CNXTID 0x00000400
186 #define CPUID2_SDBG 0x00000800
187 #define CPUID2_FMA 0x00001000
188 #define CPUID2_CX16 0x00002000
189 #define CPUID2_XTPR 0x00004000
190 #define CPUID2_PDCM 0x00008000
191 #define CPUID2_PCID 0x00020000
192 #define CPUID2_DCA 0x00040000
193 #define CPUID2_SSE41 0x00080000
194 #define CPUID2_SSE42 0x00100000
195 #define CPUID2_X2APIC 0x00200000
196 #define CPUID2_MOVBE 0x00400000
197 #define CPUID2_POPCNT 0x00800000
198 #define CPUID2_TSCDLT 0x01000000
199 #define CPUID2_AESNI 0x02000000
200 #define CPUID2_XSAVE 0x04000000
201 #define CPUID2_OSXSAVE 0x08000000
202 #define CPUID2_AVX 0x10000000
203 #define CPUID2_F16C 0x20000000
204 #define CPUID2_RDRAND 0x40000000
205 #define CPUID2_HV 0x80000000
209 /* Leaf 0 ebx. */
210 #define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */
217 /* Leaf 0 ecx. */
218 #define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */
225 #define CPUPT_NADDR_S 0 /* Number of Address Ranges */
226 #define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S)
228 #define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S)
231 #define CPUPT_CT_BITMAP_S 0 /* Bitmap of supported Cycle Threshold values */
232 #define CPUPT_CT_BITMAP_M (0xffff << CPUPT_CT_BITMAP_S)
234 #define CPUPT_PFE_BITMAP_M (0xffff << CPUPT_PFE_BITMAP_S)
239 #define AMDID_SYSCALL 0x00000800
240 #define AMDID_MP 0x00080000
241 #define AMDID_NX 0x00100000
242 #define AMDID_EXT_MMX 0x00400000
243 #define AMDID_FFXSR 0x02000000
244 #define AMDID_PAGE1GB 0x04000000
245 #define AMDID_RDTSCP 0x08000000
246 #define AMDID_LM 0x20000000
247 #define AMDID_EXT_3DNOW 0x40000000
248 #define AMDID_3DNOW 0x80000000
250 #define AMDID2_LAHF 0x00000001
251 #define AMDID2_CMP 0x00000002
252 #define AMDID2_SVM 0x00000004
253 #define AMDID2_EXT_APIC 0x00000008
254 #define AMDID2_CR8 0x00000010
255 #define AMDID2_ABM 0x00000020
256 #define AMDID2_SSE4A 0x00000040
257 #define AMDID2_MAS 0x00000080
258 #define AMDID2_PREFETCH 0x00000100
259 #define AMDID2_OSVW 0x00000200
260 #define AMDID2_IBS 0x00000400
261 #define AMDID2_XOP 0x00000800
262 #define AMDID2_SKINIT 0x00001000
263 #define AMDID2_WDT 0x00002000
264 #define AMDID2_LWP 0x00008000
265 #define AMDID2_FMA4 0x00010000
266 #define AMDID2_TCE 0x00020000
267 #define AMDID2_NODE_ID 0x00080000
268 #define AMDID2_TBM 0x00200000
269 #define AMDID2_TOPOLOGY 0x00400000
270 #define AMDID2_PCXC 0x00800000
271 #define AMDID2_PNXC 0x01000000
272 #define AMDID2_DBE 0x04000000
273 #define AMDID2_PTSC 0x08000000
274 #define AMDID2_PTSCEL2I 0x10000000
275 #define AMDID2_MWAITX 0x20000000
280 #define CPUID_STEPPING 0x0000000f
281 #define CPUID_MODEL 0x000000f0
282 #define CPUID_FAMILY 0x00000f00
283 #define CPUID_EXT_MODEL 0x000f0000
284 #define CPUID_EXT_FAMILY 0x0ff00000
288 ((((id) & CPUID_FAMILY) >= 0x600) ? \
289 (((id) & CPUID_EXT_MODEL) >> 12) : 0))
292 ((((id) & CPUID_FAMILY) == 0xf00) ? \
293 (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
307 #define CPUID_BRAND_INDEX 0x000000ff
308 #define CPUID_CLFUSH_SIZE 0x0000ff00
309 #define CPUID_HTT_CORES 0x00ff0000
310 #define CPUID_LOCAL_APIC_ID 0xff000000
315 #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */
316 #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */
317 #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */
318 #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */
323 #define MWAIT_C0 0xf0
324 #define MWAIT_C1 0x00
325 #define MWAIT_C2 0x10
326 #define MWAIT_C3 0x20
327 #define MWAIT_C4 0x30
333 #define MWAIT_INTRBREAK 0x00000001
339 #define CPUTPM1_SENSOR 0x00000001
340 #define CPUTPM1_TURBO 0x00000002
341 #define CPUTPM1_ARAT 0x00000004
342 #define CPUTPM1_PLN 0x00000010
343 #define CPUTPM1_ECMD 0x00000020
344 #define CPUTPM1_PTM 0x00000040
345 #define CPUTPM1_HWP 0x00000080
346 #define CPUTPM1_HWP_NOTIFICATION 0x00000100
347 #define CPUTPM1_HWP_ACTIVITY_WINDOW 0x00000200
348 #define CPUTPM1_HWP_PERF_PREF 0x00000400
349 #define CPUTPM1_HWP_PKG 0x00000800
350 #define CPUTPM1_HDC 0x00002000
351 #define CPUTPM1_TURBO30 0x00004000
352 #define CPUTPM1_HWP_CAPABILITIES 0x00008000
353 #define CPUTPM1_HWP_PECI_OVR 0x00010000
354 #define CPUTPM1_HWP_FLEXIBLE 0x00020000
355 #define CPUTPM1_HWP_FAST_MSR 0x00040000
356 #define CPUTPM1_HW_FEEDBACK 0x00080000
357 #define CPUTPM1_HWP_IGN_IDLE 0x00100000
358 #define CPUTPM1_THREAD_DIRECTOR 0x00800000
361 #define CPUTPM_B_NSENSINTTHRESH 0x0000000f
364 #define CPUID_PERF_STAT 0x00000001
365 #define CPUID_PERF_BIAS 0x00000008
366 #define CPUID_PERF_TD_CLASSES 0x0000ff00
369 #define CPUID_HF_PERFORMANCE 0x00000001
370 #define CPUID_HF_EFFICIENCY 0x00000002
371 #define CPUID_TD_CAPABLITIES 0x0000000f
372 #define CPUID_TD_TBLPAGES 0x00000f00
375 * CPUID instruction 0xb ebx info.
377 #define CPUID_TYPE_INVAL 0
382 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
384 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001
385 #define CPUID_EXTSTATE_XSAVEC 0x00000002
386 #define CPUID_EXTSTATE_XINUSE 0x00000004
387 #define CPUID_EXTSTATE_XSAVES 0x00000008
390 * CPUID instruction 0xd Processor Extended State Enumeration
393 #define CPUID_EXTSTATE_SUPERVISOR 0x00000001
394 #define CPUID_EXTSTATE_ALIGNED 0x00000002
395 #define CPUID_EXTSTATE_XFD_SUPPORTED 0x00000004
400 #define AMDRAS_MCA_OF_RECOV 0x00000001
401 #define AMDRAS_SUCCOR 0x00000002
402 #define AMDRAS_HW_ASSERT 0x00000004
403 #define AMDRAS_SCALABLE_MCA 0x00000008
404 #define AMDRAS_PFEH_SUPPORT 0x00000010
409 #define AMDPM_TS 0x00000001
410 #define AMDPM_FID 0x00000002
411 #define AMDPM_VID 0x00000004
412 #define AMDPM_TTP 0x00000008
413 #define AMDPM_TM 0x00000010
414 #define AMDPM_STC 0x00000020
415 #define AMDPM_100MHZ_STEPS 0x00000040
416 #define AMDPM_HW_PSTATE 0x00000080
417 #define AMDPM_TSC_INVARIANT 0x00000100
418 #define AMDPM_CPB 0x00000200
423 #define AMDFEID_CLZERO 0x00000001
424 #define AMDFEID_IRPERF 0x00000002
425 #define AMDFEID_XSAVEERPTR 0x00000004
426 #define AMDFEID_INVLPGB 0x00000008
427 #define AMDFEID_RDPRU 0x00000010
428 #define AMDFEID_BE 0x00000040
429 #define AMDFEID_MCOMMIT 0x00000100
430 #define AMDFEID_WBNOINVD 0x00000200
431 #define AMDFEID_IBPB 0x00001000
432 #define AMDFEID_INT_WBINVD 0x00002000
433 #define AMDFEID_IBRS 0x00004000
434 #define AMDFEID_STIBP 0x00008000
436 #define AMDFEID_IBRS_ALWAYSON 0x00010000
437 #define AMDFEID_STIBP_ALWAYSON 0x00020000
438 #define AMDFEID_PREFER_IBRS 0x00040000
439 #define AMDFEID_SAMEMODE_IBRS 0x00080000
440 #define AMDFEID_NO_LMSLE 0x00100000
441 #define AMDFEID_INVLPGB_NEST 0x00200000
442 #define AMDFEID_PPIN 0x00800000
443 #define AMDFEID_SSBD 0x01000000
444 /* SSBD via MSRC001_011F instead of MSR 0x48: */
445 #define AMDFEID_VIRT_SSBD 0x02000000
446 #define AMDFEID_SSB_NO 0x04000000
447 #define AMDFEID_CPPC 0x08000000
448 #define AMDFEID_PSFD 0x10000000
449 #define AMDFEID_BTC_NO 0x20000000
450 #define AMDFEID_IBPB_RET 0x40000000
455 #define AMDID_CMP_CORES 0x000000ff
456 #define AMDID_COREID_SIZE 0x0000f000
462 #define AMDID_INVLPGB_MAXCNT 0x0000ffff
464 #define AMDID_RDPRU_ID 0xffff0000
467 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
469 #define CPUID_STDEXT_FSGSBASE 0x00000001
470 #define CPUID_STDEXT_TSC_ADJUST 0x00000002
471 #define CPUID_STDEXT_SGX 0x00000004
472 #define CPUID_STDEXT_BMI1 0x00000008
473 #define CPUID_STDEXT_HLE 0x00000010
474 #define CPUID_STDEXT_AVX2 0x00000020
475 #define CPUID_STDEXT_FDP_EXC 0x00000040
476 #define CPUID_STDEXT_SMEP 0x00000080
477 #define CPUID_STDEXT_BMI2 0x00000100
478 #define CPUID_STDEXT_ERMS 0x00000200
479 #define CPUID_STDEXT_INVPCID 0x00000400
480 #define CPUID_STDEXT_RTM 0x00000800
481 #define CPUID_STDEXT_PQM 0x00001000
482 #define CPUID_STDEXT_NFPUSG 0x00002000
483 #define CPUID_STDEXT_MPX 0x00004000
484 #define CPUID_STDEXT_PQE 0x00008000
485 #define CPUID_STDEXT_AVX512F 0x00010000
486 #define CPUID_STDEXT_AVX512DQ 0x00020000
487 #define CPUID_STDEXT_RDSEED 0x00040000
488 #define CPUID_STDEXT_ADX 0x00080000
489 #define CPUID_STDEXT_SMAP 0x00100000
490 #define CPUID_STDEXT_AVX512IFMA 0x00200000
492 #define CPUID_STDEXT_CLFLUSHOPT 0x00800000
493 #define CPUID_STDEXT_CLWB 0x01000000
494 #define CPUID_STDEXT_PROCTRACE 0x02000000
495 #define CPUID_STDEXT_AVX512PF 0x04000000
496 #define CPUID_STDEXT_AVX512ER 0x08000000
497 #define CPUID_STDEXT_AVX512CD 0x10000000
498 #define CPUID_STDEXT_SHA 0x20000000
499 #define CPUID_STDEXT_AVX512BW 0x40000000
500 #define CPUID_STDEXT_AVX512VL 0x80000000
503 * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
505 #define CPUID_STDEXT2_PREFETCHWT1 0x00000001
506 #define CPUID_STDEXT2_AVX512VBMI 0x00000002
507 #define CPUID_STDEXT2_UMIP 0x00000004
508 #define CPUID_STDEXT2_PKU 0x00000008
509 #define CPUID_STDEXT2_OSPKE 0x00000010
510 #define CPUID_STDEXT2_WAITPKG 0x00000020
511 #define CPUID_STDEXT2_AVX512VBMI2 0x00000040
512 #define CPUID_STDEXT2_GFNI 0x00000100
513 #define CPUID_STDEXT2_VAES 0x00000200
514 #define CPUID_STDEXT2_VPCLMULQDQ 0x00000400
515 #define CPUID_STDEXT2_AVX512VNNI 0x00000800
516 #define CPUID_STDEXT2_AVX512BITALG 0x00001000
517 #define CPUID_STDEXT2_TME 0x00002000
518 #define CPUID_STDEXT2_AVX512VPOPCNTDQ 0x00004000
519 #define CPUID_STDEXT2_LA57 0x00010000
520 #define CPUID_STDEXT2_RDPID 0x00400000
521 #define CPUID_STDEXT2_CLDEMOTE 0x02000000
522 #define CPUID_STDEXT2_MOVDIRI 0x08000000
523 #define CPUID_STDEXT2_MOVDIR64B 0x10000000
524 #define CPUID_STDEXT2_ENQCMD 0x20000000
525 #define CPUID_STDEXT2_SGXLC 0x40000000
528 * CPUID instruction 7 Structured Extended Features, leaf 0 edx info
530 #define CPUID_STDEXT3_AVX5124VNNIW 0x00000004
531 #define CPUID_STDEXT3_AVX5124FMAPS 0x00000008
532 #define CPUID_STDEXT3_FSRM 0x00000010
533 #define CPUID_STDEXT3_AVX512VP2INTERSECT 0x00000100
534 #define CPUID_STDEXT3_MCUOPT 0x00000200
535 #define CPUID_STDEXT3_MD_CLEAR 0x00000400
536 #define CPUID_STDEXT3_TSXFA 0x00002000
537 #define CPUID_STDEXT3_PCONFIG 0x00040000
538 #define CPUID_STDEXT3_IBPB 0x04000000
539 #define CPUID_STDEXT3_STIBP 0x08000000
540 #define CPUID_STDEXT3_L1D_FLUSH 0x10000000
541 #define CPUID_STDEXT3_ARCH_CAP 0x20000000
542 #define CPUID_STDEXT3_CORE_CAP 0x40000000
543 #define CPUID_STDEXT3_SSBD 0x80000000
548 #define CPUID_STDEXT4_LASS 0x00000040
549 #define CPUID_STDEXT4_LAM 0x04000000
551 /* CPUID_HYBRID_ID leaf 0x1a */
552 #define CPUID_HYBRID_CORE_MASK 0xff000000
553 #define CPUID_HYBRID_SMALL_CORE 0x20000000
554 #define CPUID_HYBRID_LARGE_CORE 0x40000000
557 #define IA32_ARCH_CAP_RDCL_NO 0x00000001
558 #define IA32_ARCH_CAP_IBRS_ALL 0x00000002
559 #define IA32_ARCH_CAP_RSBA 0x00000004
560 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008
561 #define IA32_ARCH_CAP_SSB_NO 0x00000010
562 #define IA32_ARCH_CAP_MDS_NO 0x00000020
563 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x00000040
564 #define IA32_ARCH_CAP_TSX_CTRL 0x00000080
565 #define IA32_ARCH_CAP_TAA_NO 0x00000100
568 #define IA32_TSX_CTRL_RTM_DISABLE 0x00000001
569 #define IA32_TSX_CTRL_TSX_CPUID_CLEAR 0x00000002
589 #define MSR_P5_MC_ADDR 0x000
590 #define MSR_P5_MC_TYPE 0x001
591 #define MSR_TSC 0x010
592 #define MSR_P5_CESR 0x011
593 #define MSR_P5_CTR0 0x012
594 #define MSR_P5_CTR1 0x013
595 #define MSR_IA32_PLATFORM_ID 0x017
596 #define MSR_APICBASE 0x01b
597 #define MSR_EBL_CR_POWERON 0x02a
598 #define MSR_TEST_CTL 0x033
599 #define MSR_IA32_FEATURE_CONTROL 0x03a
600 #define MSR_IA32_SPEC_CTRL 0x048
601 #define MSR_IA32_PRED_CMD 0x049
602 #define MSR_BIOS_UPDT_TRIG 0x079
603 #define MSR_BBL_CR_D0 0x088
604 #define MSR_BBL_CR_D1 0x089
605 #define MSR_BBL_CR_D2 0x08a
606 #define MSR_BIOS_SIGN 0x08b
607 #define MSR_PERFCTR0 0x0c1
608 #define MSR_PERFCTR1 0x0c2
609 #define MSR_PLATFORM_INFO 0x0ce
610 #define MSR_MPERF 0x0e7
611 #define MSR_APERF 0x0e8
612 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
613 #define MSR_MTRRcap 0x0fe
614 #define MSR_IA32_ARCH_CAP 0x10a
615 #define MSR_IA32_FLUSH_CMD 0x10b
616 #define MSR_TSX_FORCE_ABORT 0x10f
617 #define MSR_BBL_CR_ADDR 0x116
618 #define MSR_BBL_CR_DECC 0x118
619 #define MSR_BBL_CR_CTL 0x119
620 #define MSR_BBL_CR_TRIG 0x11a
621 #define MSR_BBL_CR_BUSY 0x11b
622 #define MSR_BBL_CR_CTL3 0x11e
623 #define MSR_IA32_TSX_CTRL 0x122
624 #define MSR_IA32_MCU_OPT_CTRL 0x123
625 #define MSR_MISC_FEATURE_ENABLES 0x140
626 #define MSR_SYSENTER_CS_MSR 0x174
627 #define MSR_SYSENTER_ESP_MSR 0x175
628 #define MSR_SYSENTER_EIP_MSR 0x176
629 #define MSR_MCG_CAP 0x179
630 #define MSR_MCG_STATUS 0x17a
631 #define MSR_MCG_CTL 0x17b
632 #define MSR_EVNTSEL0 0x186
633 #define MSR_EVNTSEL1 0x187
634 #define MSR_THERM_CONTROL 0x19a
635 #define MSR_THERM_INTERRUPT 0x19b
636 #define MSR_THERM_STATUS 0x19c
637 #define MSR_IA32_MISC_ENABLE 0x1a0
638 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2
639 #define MSR_TURBO_RATIO_LIMIT 0x1ad
640 #define MSR_TURBO_RATIO_LIMIT1 0x1ae
641 #define MSR_IA32_ENERGY_PERF_BIAS 0x1b0
642 #define MSR_IA32_PKG_THERM_STATUS 0x1b1
643 #define MSR_IA32_PKG_THERM_INTERRUPT 0x1b2
644 #define MSR_DEBUGCTLMSR 0x1d9
645 #define MSR_LASTBRANCHFROMIP 0x1db
646 #define MSR_LASTBRANCHTOIP 0x1dc
647 #define MSR_LASTINTFROMIP 0x1dd
648 #define MSR_LASTINTTOIP 0x1de
649 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
650 #define MSR_MTRRVarBase 0x200
651 #define MSR_MTRR64kBase 0x250
652 #define MSR_MTRR16kBase 0x258
653 #define MSR_MTRR4kBase 0x268
654 #define MSR_PAT 0x277
655 #define MSR_MC0_CTL2 0x280
656 #define MSR_MTRRdefType 0x2ff
657 #define MSR_MC0_CTL 0x400
658 #define MSR_MC0_STATUS 0x401
659 #define MSR_MC0_ADDR 0x402
660 #define MSR_MC0_MISC 0x403
661 #define MSR_MC1_CTL 0x404
662 #define MSR_MC1_STATUS 0x405
663 #define MSR_MC1_ADDR 0x406
664 #define MSR_MC1_MISC 0x407
665 #define MSR_MC2_CTL 0x408
666 #define MSR_MC2_STATUS 0x409
667 #define MSR_MC2_ADDR 0x40a
668 #define MSR_MC2_MISC 0x40b
669 #define MSR_MC3_CTL 0x40c
670 #define MSR_MC3_STATUS 0x40d
671 #define MSR_MC3_ADDR 0x40e
672 #define MSR_MC3_MISC 0x40f
673 #define MSR_MC4_CTL 0x410
674 #define MSR_MC4_STATUS 0x411
675 #define MSR_MC4_ADDR 0x412
676 #define MSR_MC4_MISC 0x413
677 #define MSR_MCG_EXT_CTL 0x4d0
678 #define MSR_RAPL_POWER_UNIT 0x606
679 #define MSR_PKG_ENERGY_STATUS 0x611
680 #define MSR_DRAM_ENERGY_STATUS 0x619
681 #define MSR_PP0_ENERGY_STATUS 0x639
682 #define MSR_PP1_ENERGY_STATUS 0x641
683 #define MSR_PPERF 0x64e
684 #define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */
685 #define MSR_IA32_PM_ENABLE 0x770
686 #define MSR_IA32_HWP_CAPABILITIES 0x771
687 #define MSR_IA32_HWP_REQUEST_PKG 0x772
688 #define MSR_IA32_HWP_INTERRUPT 0x773
689 #define MSR_IA32_HWP_REQUEST 0x774
690 #define MSR_IA32_HWP_STATUS 0x777
695 #define MSR_VMX_BASIC 0x480
696 #define MSR_VMX_PINBASED_CTLS 0x481
697 #define MSR_VMX_PROCBASED_CTLS 0x482
698 #define MSR_VMX_EXIT_CTLS 0x483
699 #define MSR_VMX_ENTRY_CTLS 0x484
700 #define MSR_VMX_CR0_FIXED0 0x486
701 #define MSR_VMX_CR0_FIXED1 0x487
702 #define MSR_VMX_CR4_FIXED0 0x488
703 #define MSR_VMX_CR4_FIXED1 0x489
704 #define MSR_VMX_PROCBASED_CTLS2 0x48b
705 #define MSR_VMX_EPT_VPID_CAP 0x48c
706 #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d
707 #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e
708 #define MSR_VMX_TRUE_EXIT_CTLS 0x48f
709 #define MSR_VMX_TRUE_ENTRY_CTLS 0x490
715 #define MSR_APIC_000 0x800
716 #define MSR_APIC_ID 0x802
717 #define MSR_APIC_VERSION 0x803
718 #define MSR_APIC_TPR 0x808
719 #define MSR_APIC_EOI 0x80b
720 #define MSR_APIC_LDR 0x80d
721 #define MSR_APIC_SVR 0x80f
722 #define MSR_APIC_ISR0 0x810
723 #define MSR_APIC_ISR1 0x811
724 #define MSR_APIC_ISR2 0x812
725 #define MSR_APIC_ISR3 0x813
726 #define MSR_APIC_ISR4 0x814
727 #define MSR_APIC_ISR5 0x815
728 #define MSR_APIC_ISR6 0x816
729 #define MSR_APIC_ISR7 0x817
730 #define MSR_APIC_TMR0 0x818
731 #define MSR_APIC_IRR0 0x820
732 #define MSR_APIC_ESR 0x828
733 #define MSR_APIC_LVT_CMCI 0x82F
734 #define MSR_APIC_ICR 0x830
735 #define MSR_APIC_LVT_TIMER 0x832
736 #define MSR_APIC_LVT_THERMAL 0x833
737 #define MSR_APIC_LVT_PCINT 0x834
738 #define MSR_APIC_LVT_LINT0 0x835
739 #define MSR_APIC_LVT_LINT1 0x836
740 #define MSR_APIC_LVT_ERROR 0x837
741 #define MSR_APIC_ICR_TIMER 0x838
742 #define MSR_APIC_CCR_TIMER 0x839
743 #define MSR_APIC_DCR_TIMER 0x83e
744 #define MSR_APIC_SELF_IPI 0x83f
746 #define MSR_IA32_XSS 0xda0
751 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 /* Trace Output Base Register (R/W) */
752 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x561 /* Trace Output Mask Pointers Register (R/W) */
753 #define MSR_IA32_RTIT_CTL 0x570 /* Trace Control Register (R/W) */
754 #define RTIT_CTL_TRACEEN (1 << 0)
770 #define RTIT_CTL_MTC_FREQ_M (0xf << RTIT_CTL_MTC_FREQ_S)
772 #define RTIT_CTL_CYC_THRESH_M (0xf << RTIT_CTL_CYC_THRESH_S)
774 #define RTIT_CTL_PSB_FREQ_M (0xf << RTIT_CTL_PSB_FREQ_S)
777 #define RTIT_CTL_ADDR0_CFG_M (0xfULL << RTIT_CTL_ADDR0_CFG_S)
779 #define RTIT_CTL_ADDR1_CFG_M (0xfULL << RTIT_CTL_ADDR1_CFG_S)
781 #define RTIT_CTL_ADDR2_CFG_M (0xfULL << RTIT_CTL_ADDR2_CFG_S)
783 #define RTIT_CTL_ADDR3_CFG_M (0xfULL << RTIT_CTL_ADDR3_CFG_S)
784 #define MSR_IA32_RTIT_STATUS 0x571 /* Tracing Status Register (R/W) */
785 #define RTIT_STATUS_FILTEREN (1 << 0)
791 #define RTIT_STATUS_PACKETBYTECNT_M (0x1ffffULL << RTIT_STATUS_PACKETBYTECNT_S)
792 #define MSR_IA32_RTIT_CR3_MATCH 0x572 /* Trace Filter CR3 Match Register (R/W) */
793 #define MSR_IA32_RTIT_ADDR_A(n) (0x580 + (n) * 2)
794 #define MSR_IA32_RTIT_ADDR_B(n) (0x581 + (n) * 2)
795 #define MSR_IA32_RTIT_ADDR0_A 0x580 /* Region 0 Start Address (R/W) */
796 #define MSR_IA32_RTIT_ADDR0_B 0x581 /* Region 0 End Address (R/W) */
797 #define MSR_IA32_RTIT_ADDR1_A 0x582 /* Region 1 Start Address (R/W) */
798 #define MSR_IA32_RTIT_ADDR1_B 0x583 /* Region 1 End Address (R/W) */
799 #define MSR_IA32_RTIT_ADDR2_A 0x584 /* Region 2 Start Address (R/W) */
800 #define MSR_IA32_RTIT_ADDR2_B 0x585 /* Region 2 End Address (R/W) */
801 #define MSR_IA32_RTIT_ADDR3_A 0x586 /* Region 3 Start Address (R/W) */
802 #define MSR_IA32_RTIT_ADDR3_B 0x587 /* Region 3 End Address (R/W) */
806 #define TOPA_SIZE_M (0xf << TOPA_SIZE_S)
807 #define TOPA_SIZE_4K (0 << TOPA_SIZE_S)
825 #define TOPA_END (1 << 0)
830 #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
831 #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
832 #define MSR_IA32_THREAD_FEEDBACK_CHAR 0x17d2
833 #define MSR_IA32_HW_FEEDBACK_THREAD_CONFIG 0x17d4
838 #define APICBASE_RESERVED 0x000002ff
839 #define APICBASE_BSP 0x00000100
840 #define APICBASE_X2APIC 0x00000400
841 #define APICBASE_ENABLED 0x00000800
842 #define APICBASE_ADDRESS 0xfffff000
845 #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */
846 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */
847 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */
848 #define IA32_FEATURE_CONTROL_LMCE_EN 0x100000 /* enable local MCE */
851 #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL
852 #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL
853 #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL
854 #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL
855 #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL
856 #define IA32_MISC_EN_MONE 0x0000000000040000ULL
857 #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL
858 #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL
859 #define IA32_MISC_EN_XDD 0x0000000400000000ULL
870 #define IA32_SPEC_CTRL_IBRS 0x00000001
871 #define IA32_SPEC_CTRL_STIBP 0x00000002
872 #define IA32_SPEC_CTRL_SSBD 0x00000004
875 #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
878 #define IA32_FLUSH_CMD_L1D 0x00000001
881 #define IA32_RNGDS_MITG_DIS 0x00000001
884 #define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff)
885 #define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff)
886 #define IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff)
887 #define IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff)
896 #define IA32_HWP_ACTIVITY_WINDOW (0x3ffULL << 32)
897 #define IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE (0xffULL << 24)
898 #define IA32_HWP_DESIRED_PERFORMANCE (0xffULL << 16)
899 #define IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE (0xffULL << 8)
900 #define IA32_HWP_MINIMUM_PERFORMANCE (0xffULL << 0)
903 #define IA32_ENERGY_PERF_BIAS_POLICY_HINT_MASK (0xfULL << 0)
906 #define IA32_HW_FEEDBACK_PTR_ENABLE (0x1ULL << 0)
909 #define IA32_HW_FEEDBACK_CONFIG_EN_HFI (0x1ULL << 0)
910 #define IA32_HW_FEEDBACK_CONFIG_EN_THDIR (0x1ULL << 1)
913 #define IA32_PKG_THERM_STATUS_HFI_UPDATED (0x1ULL << 26)
916 #define IA32_PKG_THERM_INTERRUPT_HFI_ENABLE (0x1ULL << 25)
921 #define PAT_UNCACHEABLE 0x00
922 #define PAT_WRITE_COMBINING 0x01
923 #define PAT_WRITE_THROUGH 0x04
924 #define PAT_WRITE_PROTECTED 0x05
925 #define PAT_WRITE_BACK 0x06
926 #define PAT_UNCACHED 0x07
928 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
933 #define MTRR_UNCACHEABLE 0x00
934 #define MTRR_WRITE_COMBINING 0x01
935 #define MTRR_WRITE_THROUGH 0x04
936 #define MTRR_WRITE_PROTECTED 0x05
937 #define MTRR_WRITE_BACK 0x06
941 #define MTRR_CAP_WC 0x0000000000000400
942 #define MTRR_CAP_FIXED 0x0000000000000100
943 #define MTRR_CAP_VCNT 0x00000000000000ff
944 #define MTRR_DEF_ENABLE 0x0000000000000800
945 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
946 #define MTRR_DEF_TYPE 0x00000000000000ff
947 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
948 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff
949 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
950 #define MTRR_PHYSMASK_VALID 0x0000000000000800
955 #define CCR0 0xc0 /* Configuration control register 0 */
956 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
958 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
959 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
960 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
961 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
962 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
964 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
966 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
968 #define CCR1 0xc1 /* Configuration control register 1 */
969 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
970 #define CCR1_SMI 0x02 /* Enables SMM pins */
971 #define CCR1_SMAC 0x04 /* System management memory access */
972 #define CCR1_MMAC 0x08 /* Main memory access */
973 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
974 #define CCR1_SM3 0x80 /* SMM address space address region 3 */
976 #define CCR2 0xc2
977 #define CCR2_WB 0x02 /* Enables WB cache interface pins */
978 #define CCR2_SADS 0x02 /* Slow ADS */
979 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
980 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
981 #define CCR2_WT1 0x10 /* WT region 1 */
982 #define CCR2_WPR1 0x10 /* Write-protect region 1 */
983 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
985 #define CCR2_BWRT 0x40 /* Enables burst write cycles */
986 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
988 #define CCR3 0xc3
989 #define CCR3_SMILOCK 0x01 /* SMM register lock */
990 #define CCR3_NMI 0x02 /* Enables NMI during SMM */
991 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */
992 #define CCR3_SMMMODE 0x08 /* SMM Mode */
993 #define CCR3_MAPEN0 0x10 /* Enables Map0 */
994 #define CCR3_MAPEN1 0x20 /* Enables Map1 */
995 #define CCR3_MAPEN2 0x40 /* Enables Map2 */
996 #define CCR3_MAPEN3 0x80 /* Enables Map3 */
998 #define CCR4 0xe8
999 #define CCR4_IOMASK 0x07
1000 #define CCR4_MEM 0x08 /* Enables memory bypassing */
1001 #define CCR4_DTE 0x10 /* Enables directory table entry cache */
1002 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */
1003 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
1005 #define CCR5 0xe9
1006 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
1007 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
1008 #define CCR5_LBR1 0x10 /* Local bus region 1 */
1009 #define CCR5_ARREN 0x20 /* Enables ARR region */
1011 #define CCR6 0xea
1013 #define CCR7 0xeb
1016 #define PCR0 0x20
1017 #define PCR0_RSTK 0x01 /* Enables return stack */
1018 #define PCR0_BTB 0x02 /* Enables branch target buffer */
1019 #define PCR0_LOOP 0x04 /* Enables loop */
1020 #define PCR0_AIS 0x08 /* Enables all instructions stalled to
1022 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
1023 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
1024 #define PCR0_LSSER 0x80 /* Disable reorder */
1027 #define DIR0 0xfe
1028 #define DIR1 0xff
1033 #define MCG_CAP_COUNT 0x000000ff
1034 #define MCG_CAP_CTL_P 0x00000100
1035 #define MCG_CAP_EXT_P 0x00000200
1036 #define MCG_CAP_CMCI_P 0x00000400
1037 #define MCG_CAP_TES_P 0x00000800
1038 #define MCG_CAP_EXT_CNT 0x00ff0000
1039 #define MCG_CAP_SER_P 0x01000000
1040 #define MCG_CAP_EMC_P 0x02000000
1041 #define MCG_CAP_ELOG_P 0x04000000
1042 #define MCG_CAP_LMCE_P 0x08000000
1043 #define MCG_STATUS_RIPV 0x00000001
1044 #define MCG_STATUS_EIPV 0x00000002
1045 #define MCG_STATUS_MCIP 0x00000004
1046 #define MCG_STATUS_LMCS 0x00000008 /* if MCG_CAP_LMCE_P */
1047 #define MCG_CTL_ENABLE 0xffffffffffffffff
1048 #define MCG_CTL_DISABLE 0x0000000000000000
1054 #define MC_STATUS_MCA_ERROR 0x000000000000ffff
1055 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
1056 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000
1057 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */
1058 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
1059 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */
1060 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */
1061 #define MC_STATUS_PCC 0x0200000000000000
1062 #define MC_STATUS_ADDRV 0x0400000000000000
1063 #define MC_STATUS_MISCV 0x0800000000000000
1064 #define MC_STATUS_EN 0x1000000000000000
1065 #define MC_STATUS_UC 0x2000000000000000
1066 #define MC_STATUS_OVER 0x4000000000000000
1067 #define MC_STATUS_VAL 0x8000000000000000
1068 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
1069 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
1070 #define MC_MISC_PCIE_RID 0x00000000ffff0000
1071 #define MC_MISC_PCIE_FUNC 0x0000000000070000
1072 #define MC_MISC_PCIE_SLOT 0x0000000000f80000
1073 #define MC_MISC_PCIE_BUS 0x00000000ff000000
1074 #define MC_MISC_PCIE_SEG 0x000000ff00000000
1075 #define MC_CTL2_THRESHOLD 0x0000000000007fff
1076 #define MC_CTL2_CMCI_EN 0x0000000040000000
1078 #define MC_MISC_AMD_VAL 0x8000000000000000 /* Counter presence valid */
1079 #define MC_MISC_AMD_CNTP 0x4000000000000000 /* Counter present */
1080 #define MC_MISC_AMD_LOCK 0x2000000000000000 /* Register locked */
1081 #define MC_MISC_AMD_INTP 0x1000000000000000 /* Int. type can generate interrupts */
1082 #define MC_MISC_AMD_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */
1084 #define MC_MISC_AMD_CNTEN 0x0008000000000000 /* Counter enabled */
1085 #define MC_MISC_AMD_INT_MASK 0x0006000000000000 /* Interrupt type */
1086 #define MC_MISC_AMD_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */
1087 #define MC_MISC_AMD_INT_SMI 0x0004000000000000 /* SMI */
1088 #define MC_MISC_AMD_OVERFLOW 0x0001000000000000 /* Counter overflow */
1089 #define MC_MISC_AMD_CNT_MASK 0x00000fff00000000 /* Counter value */
1091 #define MC_MISC_AMD_CNT_MAX 0xfff
1092 #define MC_MISC_AMD_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */
1096 #define MSR_SMCA_MC0_CTL 0xc0002000
1097 #define MSR_SMCA_MC0_STATUS 0xc0002001
1098 #define MSR_SMCA_MC0_ADDR 0xc0002002
1099 #define MSR_SMCA_MC0_MISC0 0xc0002003
1100 #define MSR_SMCA_MC_CTL(x) (MSR_SMCA_MC0_CTL + 0x10 * (x))
1101 #define MSR_SMCA_MC_STATUS(x) (MSR_SMCA_MC0_STATUS + 0x10 * (x))
1102 #define MSR_SMCA_MC_ADDR(x) (MSR_SMCA_MC0_ADDR + 0x10 * (x))
1103 #define MSR_SMCA_MC_MISC(x) (MSR_SMCA_MC0_MISC0 + 0x10 * (x))
1109 * NCRx+0: A31-A24 of starting address
1116 #define NCR1 0xc4
1117 #define NCR2 0xc7
1118 #define NCR3 0xca
1119 #define NCR4 0xcd
1121 #define NCR_SIZE_0K 0
1142 * ARRx + 0: A31-A24 of start address
1146 #define ARR0 0xc4
1147 #define ARR1 0xc7
1148 #define ARR2 0xca
1149 #define ARR3 0xcd
1150 #define ARR4 0xd0
1151 #define ARR5 0xd3
1152 #define ARR6 0xd6
1153 #define ARR7 0xd9
1155 #define ARR_SIZE_0K 0
1176 #define RCR0 0xdc
1177 #define RCR1 0xdd
1178 #define RCR2 0xde
1179 #define RCR3 0xdf
1180 #define RCR4 0xe0
1181 #define RCR5 0xe1
1182 #define RCR6 0xe2
1183 #define RCR7 0xe3
1185 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
1186 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
1187 #define RCR_WWO 0x02 /* Weak write ordering. */
1188 #define RCR_WL 0x04 /* Weak locking. */
1189 #define RCR_WG 0x08 /* Write gathering. */
1190 #define RCR_WT 0x10 /* Write-through. */
1191 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
1194 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
1195 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
1196 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
1199 #define MSR_EFER 0xc0000080 /* extended features */
1200 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
1201 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
1202 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
1203 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
1204 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
1205 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
1206 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
1207 #define MSR_TSC_AUX 0xc0000103
1208 #define MSR_PERFEVSEL0 0xc0010000
1209 #define MSR_PERFEVSEL1 0xc0010001
1210 #define MSR_PERFEVSEL2 0xc0010002
1211 #define MSR_PERFEVSEL3 0xc0010003
1212 #define MSR_K7_PERFCTR0 0xc0010004
1213 #define MSR_K7_PERFCTR1 0xc0010005
1214 #define MSR_K7_PERFCTR2 0xc0010006
1215 #define MSR_K7_PERFCTR3 0xc0010007
1216 #define MSR_SYSCFG 0xc0010010
1217 #define MSR_HWCR 0xc0010015
1218 #define MSR_IORRBASE0 0xc0010016
1219 #define MSR_IORRMASK0 0xc0010017
1220 #define MSR_IORRBASE1 0xc0010018
1221 #define MSR_IORRMASK1 0xc0010019
1222 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
1223 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
1224 #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
1225 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
1226 #define MSR_MC0_CTL_MASK 0xc0010044
1227 #define MSR_AMDK8_IPM 0xc0010055
1228 #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
1229 #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
1230 #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
1231 #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
1232 #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
1233 #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
1234 #define MSR_VM_CR 0xc0010114 /* SVM: feature control */
1235 #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
1236 #define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */
1237 #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */
1238 #define MSR_LS_CFG 0xc0011020
1239 #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
1240 #define MSR_DE_CFG 0xc0011029 /* Decode Configuration */
1247 #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
1250 #define DE_CFG_10H_12H_STACK_POINTER_JUMP_FIX_BIT 0x1
1251 #define DE_CFG_ZEN_LOAD_STALE_DATA_FIX_BIT 0x2000
1252 #define DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 0x200
1264 #define VIA_CPUID_HAS_RNG 0x000004
1265 #define VIA_CPUID_DO_RNG 0x000008
1266 #define VIA_CPUID_HAS_ACE 0x000040
1267 #define VIA_CPUID_DO_ACE 0x000080
1268 #define VIA_CPUID_HAS_ACE2 0x000100
1269 #define VIA_CPUID_DO_ACE2 0x000200
1270 #define VIA_CPUID_HAS_PHE 0x000400
1271 #define VIA_CPUID_DO_PHE 0x000800
1272 #define VIA_CPUID_HAS_PMM 0x001000
1273 #define VIA_CPUID_DO_PMM 0x002000
1276 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
1277 #define VIA_CRYPT_CWLO_ALG_M 0x00000070
1278 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000
1279 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
1280 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
1281 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
1282 #define VIA_CRYPT_CWLO_NORMAL 0x00000000
1283 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
1284 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
1285 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200
1286 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
1287 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
1288 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */