1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
6  * Copyright (c) 2004-2005 Bruno Durcot
10  * Copyright (c) 2008-2009 Gen Otsuji
45  * 41256 Rev 3.00 - July 07, 2008
47  * Revision C1 Processors Volume 1 of 7 - Sep 29, 2024
103 	int	volts;		/* Voltage in mV. */  member
106 	int	pstate_id;	/* P-State id */
135     &hwpstate_verify, 0, "Verify P-state after setting");
140     "If enabled (1), limit administrative control of P-states to the value in "
188  * Go to Px-state on all cpus, considering the limit register (if so
210 	HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n", id, cpu);  in hwpstate_goto_pstate()
211 	/* Go To Px-state */  in hwpstate_goto_pstate()
215 	 * We are going to the same Px-state on all cpus.  in hwpstate_goto_pstate()
226 		HWPSTATE_DEBUG(dev, "setting P%d-state on cpu%d\n", id, i);  in hwpstate_goto_pstate()
227 		/* Go To Px-state */  in hwpstate_goto_pstate()
232 	 * Verify whether each core is in the requested P-state.  in hwpstate_goto_pstate()
249 			HWPSTATE_DEBUG(dev, "result: P%d-state on cpu%d\n",  in hwpstate_goto_pstate()
272 	set = sc->hwpstate_settings;  in hwpstate_set()
273 	for (i = 0; i < sc->cfnum; i++)  in hwpstate_set()
274 		if (CPUFREQ_CMP(cf->freq, set[i].freq))  in hwpstate_set()
276 	if (i == sc->cfnum)  in hwpstate_set()
293 	if (msr >= sc->cfnum)  in hwpstate_get()
295 	set = sc->hwpstate_settings[msr];  in hwpstate_get()
297 	cf->freq = set.freq;  in hwpstate_get()
298 	cf->volts = set.volts;  in hwpstate_get()
299 	cf->power = set.power;  in hwpstate_get()
300 	cf->lat = set.lat;  in hwpstate_get()
301 	cf->dev = dev;  in hwpstate_get()
315 	if (*count < sc->cfnum)  in hwpstate_settings()
317 	for (i = 0; i < sc->cfnum; i++, sets++) {  in hwpstate_settings()
318 		set = sc->hwpstate_settings[i];  in hwpstate_settings()
319 		sets->freq = set.freq;  in hwpstate_settings()
320 		sets->volts = set.volts;  in hwpstate_settings()
321 		sets->power = set.power;  in hwpstate_settings()
322 		sets->lat = set.lat;  in hwpstate_settings()
323 		sets->dev = dev;  in hwpstate_settings()
325 	*count = sc->cfnum;  in hwpstate_settings()
384 	sc->dev = dev;  in hwpstate_probe()
420 		if (sc->cfnum != 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr)) {  in hwpstate_probe()
422 			    " count mismatch\n", (intmax_t)msr, sc->cfnum);  in hwpstate_probe()
459 	sc->cfnum = 1 + AMD_10H_11H_GET_PSTATE_MAX_VAL(msr);  in hwpstate_get_info_from_msr()
460 	hwpstate_set = sc->hwpstate_settings;  in hwpstate_get_info_from_msr()
461 	for (i = 0; i < sc->cfnum; i++) {  in hwpstate_get_info_from_msr()
470 		hwpstate_set[i].volts = CPUFREQ_VAL_UNKNOWN;  in hwpstate_get_info_from_msr()
512 			hwpstate_set[i].volts =  in hwpstate_get_info_from_msr()
513 			    (155000 - (625 * AMD_17H_CUR_VID(msr))) / 100;  in hwpstate_get_info_from_msr()
517 			 * "BKDG for AMD Family 15h Models 70h-7fh Processors",  in hwpstate_get_info_from_msr()
523 			hwpstate_set[i].power *= hwpstate_set[i].volts;  in hwpstate_get_info_from_msr()
524 			/* Milli amps * milli volts to milli watts. */  in hwpstate_get_info_from_msr()
563 	sc->cfnum = count;  in hwpstate_get_info_from_acpi_perf()
564 	hwpstate_set = sc->hwpstate_settings;  in hwpstate_get_info_from_acpi_perf()
569 			hwpstate_set[i].volts = perf_set[i].volts;  in hwpstate_get_info_from_acpi_perf()