Lines Matching +full:0 +full:xfe200000
60 reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
64 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
68 bman-portal@0 {
93 buffer-pool@0 {
95 fsl,bpid = <0>;
96 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
101 qportal0: qman-portal@0 {
188 flash@0 {
192 reg = <0>;
196 reg = <0x00000000 0x00100000>;
201 reg = <0x00100000 0x00500000>;
206 reg = <0x00600000 0x00100000>;
211 reg = <0x00700000 0x00900000>;
219 reg = <0x51>;
223 reg = <0x52>;
230 reg = <0x68>;
231 interrupts = <0x1 0x1 0 0>;
237 /* fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */
238 /* fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */
243 /* fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */
244 /* fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */
249 /* fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */
261 reg = <0x8>;
272 #size-cells = <0>;
275 fsl,hydra-mdio-muxval = <0x00>;
278 phy_rgmii_0: ethernet-phy@0 {
279 reg = <0x0>;
282 reg = <0x1>;
297 #size-cells = <0>;
300 fsl,hydra-mdio-muxval = <0x00>;
304 reg = <0x1c>;
307 reg = <0x1d>;
310 reg = <0x1e>;
313 reg = <0x1f>;
352 #size-cells = <0>;
354 reg = <0xe7120 0xee0>;
355 interrupts = <100 1 0 0>;
398 reg = <0x4>;
402 phy_xgmii_2: ethernet-phy@0 {
403 reg = <0x0>;
410 reg = <0xf 0xfe0c0000 0 0x11000>;
413 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
416 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
421 reg = <0xf 0xfe124000 0 0x1000>;
422 ranges = <0 0 0xf 0xb8000000 0x04000000>;
424 flash@0,0 {
432 reg = <0 0 0x04000000>;
437 nand@2,0 {
441 reg = <0x2 0x0 0x40000>;
443 partition@0 {
445 reg = <0x0 0x02000000>;
451 reg = <0x02000000 0x10000000>;
456 reg = <0x12000000 0x08000000>;
461 reg = <0x1a000000 0x04000000>;
466 reg = <0x1e000000 0x01000000>;
471 reg = <0x1f000000 0x21000000>;
475 board-control@3,0 {
477 reg = <3 0 0x30>;
482 reg = <0xf 0xfe200000 0 0x1000>;
483 ranges = <0x02000000 0 0x80000000 0x0 0x80000000 0x0 0x10000000
484 0x01000000 0 0x00000000 0x0 0xff000000 0x0 0x00010000>;
485 pcie@0 {
486 ranges = <0x02000000 0 0x80000000
487 0x02000000 0 0x80000000
488 0 0x10000000
490 0x01000000 0 0x00000000
491 0x01000000 0 0xff000000
492 0 0x00010000>;
497 reg = <0xf 0xfe201000 0 0x1000>;
498 ranges = <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x10000000
499 0x01000000 0x0 0x00000000 0x0 0xff010000 0x0 0x00010000>;
500 pcie@0 {
501 ranges = <0x02000000 0 0x90000000
502 0x02000000 0 0x90000000
503 0 0x10000000
505 0x01000000 0 0x00000000
506 0x01000000 0 0xff010000
507 0 0x00010000>;
512 reg = <0xf 0xfe202000 0 0x1000>;
513 ranges = <0x02000000 0 0xa0000000 0x0 0xa0000000 0 0x10000000
514 0x01000000 0 0x00000000 0x0 0xff020000 0 0x00010000>;
515 pcie@0 {
516 ranges = <0x02000000 0 0xa0000000
517 0x02000000 0 0xa0000000
518 0 0x10000000
520 0x01000000 0 0x00000000
521 0x01000000 0 0xff020000
522 0 0x00010000>;
527 reg = <0xf 0xfe203000 0 0x1000>;
528 ranges = <0x02000000 0 0xb0000000 0x0 0xb0000000 0 0x08000000
529 0x01000000 0 0x00000000 0x0 0xff030000 0 0x00010000>;
530 pcie@0 {
531 ranges = <0x02000000 0 0xb0000000
532 0x02000000 0 0xb0000000
533 0 0x08000000
535 0x01000000 0 0x00000000
536 0x01000000 0 0xff030000
537 0 0x00010000>;