Lines Matching +full:usb2 +full:- +full:phy0
35 /dts-v1/;
40 #address-cells = <2>;
41 #size-cells = <2>;
54 #address-cells = <1>;
55 #size-cells = <0>;
60 next-level-cache = <&L2>;
66 next-level-cache = <&L2>;
75 #address-cells = <2>;
76 #size-cells = <1>;
77 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
80 interrupt-parent = <&mpic>;
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "cfi-flash";
92 bank-width = <2>;
93 device-width = <1>;
99 label = "NOR (RO) Vitesse-7385 Firmware";
100 read-only;
107 read-only;
114 read-only;
125 /* 512KB for u-boot Bootloader Image */
126 /* 512KB for u-boot Environment Variables */
128 label = "NOR (RO) U-Boot Image";
129 read-only;
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "fsl,p1020-fcm-nand",
137 "fsl,elbc-fcm-nand";
142 /* 1MB for u-boot Bootloader Image */
144 label = "NAND (RO) U-Boot Image";
145 read-only;
152 read-only;
159 read-only;
166 read-only;
183 #address-cells = <1>;
184 #size-cells = <1>;
185 compatible = "vitesse-7385";
192 #address-cells = <1>;
193 #size-cells = <1>;
195 compatible = "fsl,p1020-immr", "simple-bus";
197 bus-frequency = <0>; // Filled out by uboot.
199 ecm-law@0 {
200 compatible = "fsl,ecm-law";
202 fsl,num-laws = <12>;
206 compatible = "fsl,p1020-ecm", "fsl,ecm";
209 interrupt-parent = <&mpic>;
212 memory-controller@2000 {
213 compatible = "fsl,p1020-memory-controller";
215 interrupt-parent = <&mpic>;
220 #address-cells = <1>;
221 #size-cells = <0>;
222 cell-index = <0>;
223 compatible = "fsl-i2c";
226 interrupt-parent = <&mpic>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 cell-index = <1>;
238 compatible = "fsl-i2c";
241 interrupt-parent = <&mpic>;
246 cell-index = <0>;
250 clock-frequency = <0>;
252 interrupt-parent = <&mpic>;
256 cell-index = <1>;
260 clock-frequency = <0>;
262 interrupt-parent = <&mpic>;
266 cell-index = <0>;
267 #address-cells = <1>;
268 #size-cells = <0>;
272 interrupt-parent = <&mpic>;
276 #address-cells = <1>;
277 #size-cells = <1>;
278 compatible = "fsl,espi-flash";
282 spi-max-frequency = <50000000>;
286 /* 512KB for u-boot Bootloader Image */
288 label = "SPI (RO) U-Boot Image";
289 read-only;
296 read-only;
303 read-only;
310 read-only;
321 gpio: gpio-controller@f000 {
322 #gpio-cells = <2>;
323 compatible = "fsl,mpc8572-gpio";
326 interrupt-parent = <&mpic>;
327 gpio-controller;
330 L2: l2-cache-controller@20000 {
331 compatible = "fsl,p1020-l2-cache-controller";
333 cache-line-size = <32>; // 32 bytes
334 cache-size = <0x40000>; // L2,256K
335 interrupt-parent = <&mpic>;
340 #address-cells = <1>;
341 #size-cells = <1>;
342 compatible = "fsl,eloplus-dma";
345 cell-index = <0>;
346 dma-channel@0 {
347 compatible = "fsl,eloplus-dma-channel";
349 cell-index = <0>;
350 interrupt-parent = <&mpic>;
353 dma-channel@80 {
354 compatible = "fsl,eloplus-dma-channel";
356 cell-index = <1>;
357 interrupt-parent = <&mpic>;
360 dma-channel@100 {
361 compatible = "fsl,eloplus-dma-channel";
363 cell-index = <2>;
364 interrupt-parent = <&mpic>;
367 dma-channel@180 {
368 compatible = "fsl,eloplus-dma-channel";
370 cell-index = <3>;
371 interrupt-parent = <&mpic>;
377 #address-cells = <1>;
378 #size-cells = <0>;
379 compatible = "fsl,etsec2-mdio";
382 phy0: ethernet-phy@0 { label
383 interrupt-parent = <&mpic>;
388 phy1: ethernet-phy@1 {
389 interrupt-parent = <&mpic>;
396 #address-cells = <1>;
397 #size-cells = <0>;
398 compatible = "fsl,etsec2-tbi";
401 tbi0: tbi-phy@11 {
403 device_type = "tbi-phy";
408 #address-cells = <1>;
409 #size-cells = <1>;
415 local-mac-address = [ 00 00 00 00 00 00 ];
416 interrupt-parent = <&mpic>;
417 fixed-link = <1 1 1000 0 0>;
418 phy-connection-type = "rgmii-id";
420 queue-group@0 {
421 #address-cells = <1>;
422 #size-cells = <1>;
427 queue-group@1 {
428 #address-cells = <1>;
429 #size-cells = <1>;
436 #address-cells = <1>;
437 #size-cells = <1>;
443 local-mac-address = [ 00 00 00 00 00 00 ];
444 interrupt-parent = <&mpic>;
445 phy-handle = <&phy0>;
446 tbi-handle = <&tbi0>;
447 phy-connection-type = "sgmii";
449 queue-group@0 {
450 #address-cells = <1>;
451 #size-cells = <1>;
456 queue-group@1 {
457 #address-cells = <1>;
458 #size-cells = <1>;
465 #address-cells = <1>;
466 #size-cells = <1>;
472 local-mac-address = [ 00 00 00 00 00 00 ];
473 interrupt-parent = <&mpic>;
474 phy-handle = <&phy1>;
475 phy-connection-type = "rgmii-id";
477 queue-group@0 {
478 #address-cells = <1>;
479 #size-cells = <1>;
484 queue-group@1 {
485 #address-cells = <1>;
486 #size-cells = <1>;
493 #address-cells = <1>;
494 #size-cells = <0>;
495 compatible = "fsl-usb2-dr";
497 interrupt-parent = <&mpic>;
502 /* USB2 is shared with localbus, so it must be disabled
504 since U-Boot doesn't clear the status property when
505 it enables USB2. OTOH, U-Boot does create a new node
508 #address-cells = <1>;
509 #size-cells = <0>;
510 compatible = "fsl-usb2-dr";
512 interrupt-parent = <&mpic>;
519 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
522 interrupt-parent = <&mpic>;
523 /* Filled in by U-Boot */
524 clock-frequency = <0>;
532 interrupt-parent = <&mpic>;
533 fsl,num-channels = <4>;
534 fsl,channel-fifo-len = <24>;
535 fsl,exec-units-mask = <0xbfe>;
536 fsl,descriptor-types-mask = <0x3ab0ebf>;
540 interrupt-controller;
541 #address-cells = <0>;
542 #interrupt-cells = <2>;
544 compatible = "chrp,open-pic";
545 device_type = "open-pic";
549 compatible = "fsl,p1020-msi", "fsl,mpic-msi";
551 msi-available-ranges = <0 0x100>;
561 interrupt-parent = <&mpic>;
564 global-utilities@e0000 { //global utilities block
565 compatible = "fsl,p1020-guts";
567 fsl,has-rstcr;
572 compatible = "fsl,mpc8548-pcie";
574 #interrupt-cells = <1>;
575 #size-cells = <2>;
576 #address-cells = <3>;
578 bus-range = <0 255>;
581 clock-frequency = <33333333>;
582 interrupt-parent = <&mpic>;
586 #size-cells = <2>;
587 #address-cells = <3>;
600 compatible = "fsl,mpc8548-pcie";
602 #interrupt-cells = <1>;
603 #size-cells = <2>;
604 #address-cells = <3>;
606 bus-range = <0 255>;
609 clock-frequency = <33333333>;
610 interrupt-parent = <&mpic>;
614 #size-cells = <2>;
615 #address-cells = <3>;