Lines Matching +full:0 +full:x00000400
35 #define AVR32_CTRL 0x00 /* Control */
36 #define AVR32_CTRL_DEV_ADDR 0x7F
37 #define AVR32_CTRL_DEV_FADDR_EN 0x80
38 #define AVR32_CTRL_DEV_EN_USBA 0x100
39 #define AVR32_CTRL_DEV_DETACH 0x200
40 #define AVR32_CTRL_DEV_REWAKEUP 0x400
42 #define AVR32_FNUM 0x04 /* Frame Number */
43 #define AVR32_FNUM_MASK 0x3FFF
44 #define AVR32_FRAME_MASK 0x7FF
46 /* 0x08 - 0x0C Reserved */
47 #define AVR32_IEN 0x10 /* Interrupt Enable */
48 #define AVR32_INTSTA 0x14 /* Interrupt Status */
49 #define AVR32_CLRINT 0x18 /* Clear Interrupt */
51 #define AVR32_INT_SPEED 0x00000001 /* set if High Speed else Full Speed */
52 #define AVR32_INT_DET_SUSPD 0x00000002
53 #define AVR32_INT_MICRO_SOF 0x00000004
54 #define AVR32_INT_INT_SOF 0x00000008
55 #define AVR32_INT_ENDRESET 0x00000010
56 #define AVR32_INT_WAKE_UP 0x00000020
57 #define AVR32_INT_ENDOFRSM 0x00000040
58 #define AVR32_INT_UPSTR_RES 0x00000080
59 #define AVR32_INT_EPT_INT(n) (0x00000100 << (n))
60 #define AVR32_INT_DMA_INT(n) (0x01000000 << (n))
62 #define AVR32_EPTRST 0x1C /* Endpoints Reset */
63 #define AVR32_EPTRST_MASK(n) (0x00000001 << (n))
65 /* 0x20 - 0xCC Reserved */
66 #define AVR32_TSTSOFCNT 0xD0 /* Test SOF Counter */
67 #define AVR32_TSTCNTA 0xD4 /* Test A Counter */
68 #define AVR32_TSTCNTB 0xD8 /* Test B Counter */
69 #define AVR32_TSTMODEREG 0xDC /* Test Mode */
70 #define AVR32_TST 0xE0 /* Test */
71 #define AVR32_TST_NORMAL 0x00000000
72 #define AVR32_TST_HS_ONLY 0x00000002
73 #define AVR32_TST_FS_ONLY 0x00000003
75 /* 0xE4 - 0xE8 Reserved */
76 #define AVR32_IPPADDRSIZE 0xEC /* PADDRSIZE */
77 #define AVR32_IPNAME1 0xF0 /* Name1 */
78 #define AVR32_IPNAME2 0xF4 /* Name2 */
79 #define AVR32_IPFEATURES 0xF8 /* Features */
80 #define AVR32_IPFEATURES_NEP(x) (((x) & 0xF) ? ((x) & 0xF) : 0x10)
82 #define AVR32_IPVERSION 0xFC /* IP Version */
84 #define _A(base,n) ((base) + (0x20*(n)))
85 #define AVR32_EPTCFG(n) _A(0x100, n) /* Endpoint Configuration */
87 #define AVR32_EPTCFG_EPDIR_OUT 0x00000000
88 #define AVR32_EPTCFG_EPDIR_IN 0x00000008
89 #define AVR32_EPTCFG_TYPE_CTRL 0x00000000
90 #define AVR32_EPTCFG_TYPE_ISOC 0x00000100
91 #define AVR32_EPTCFG_TYPE_BULK 0x00000200
92 #define AVR32_EPTCFG_TYPE_INTR 0x00000300
93 #define AVR32_EPTCFG_NBANK(n) (0x00000400*(n))
94 #define AVR32_EPTCFG_NB_TRANS(n) (0x00001000*(n))
95 #define AVR32_EPTCFG_EPT_MAPD 0x80000000
97 #define AVR32_EPTCTLENB(n) _A(0x104, n) /* Endpoint Control Enable */
98 #define AVR32_EPTCTLDIS(n) _A(0x108, n) /* Endpoint Control Disable */
99 #define AVR32_EPTCTL(n) _A(0x10C, n) /* Endpoint Control */
100 #define AVR32_EPTCTL_EPT_ENABL 0x00000001
101 #define AVR32_EPTCTL_AUTO_VALID 0x00000002
102 #define AVR32_EPTCTL_INTDIS_DMA 0x00000008
103 #define AVR32_EPTCTL_NYET_DIS 0x00000010
104 #define AVR32_EPTCTL_DATAX_RX 0x00000040
105 #define AVR32_EPTCTL_MDATA_RX 0x00000080
106 #define AVR32_EPTCTL_ERR_OVFLW 0x00000100
107 #define AVR32_EPTCTL_RX_BK_RDY 0x00000200
108 #define AVR32_EPTCTL_TX_COMPLT 0x00000400
109 #define AVR32_EPTCTL_TX_PK_RDY 0x00000800
110 #define AVR32_EPTCTL_RX_SETUP 0x00001000
111 #define AVR32_EPTCTL_STALL_SNT 0x00002000
112 #define AVR32_EPTCTL_NAK_IN 0x00004000
113 #define AVR32_EPTCTL_NAK_OUT 0x00008000
114 #define AVR32_EPTCTL_BUSY_BANK 0x00040000
115 #define AVR32_EPTCTL_SHORT_PCKT 0x80000000
117 /* 0x110 Reserved */
118 #define AVR32_EPTSETSTA(n) _A(0x114, n) /* Endpoint Set Status */
119 #define AVR32_EPTCLRSTA(n) _A(0x118, n) /* Endpoint Clear Status */
120 #define AVR32_EPTSTA(n) _A(0x11C, n) /* Endpoint Status */
121 #define AVR32_EPTSTA_FRCESTALL 0x00000020
122 #define AVR32_EPTSTA_TOGGLESQ_STA(x) (((x) & 0xC0) >> 6)
123 #define AVR32_EPTSTA_TOGGLESQ 0x00000040
124 #define AVR32_EPTSTA_ERR_OVFLW 0x00000100
125 #define AVR32_EPTSTA_RX_BK_RDY 0x00000200
126 #define AVR32_EPTSTA_TX_COMPLT 0x00000400
127 #define AVR32_EPTSTA_TX_PK_RDY 0x00000800
128 #define AVR32_EPTSTA_RX_SETUP 0x00001000
129 #define AVR32_EPTSTA_STALL_SNT 0x00002000
130 #define AVR32_EPTSTA_NAK_IN 0x00004000
131 #define AVR32_EPTSTA_NAK_OUT 0x00008000
132 #define AVR32_EPTSTA_CURRENT_BANK(x) (((x) & 0x00030000) >> 16)
133 #define AVR32_EPTSTA_BUSY_BANK_STA(x) (((x) & 0x000C0000) >> 18)
134 #define AVR32_EPTSTA_BYTE_COUNT(x) (((x) & 0x7FF00000) >> 20)
135 #define AVR32_EPTSTA_SHRT_PCKT 0x80000000
137 /* 0x300 - 0x30C Reserved */
138 #define AVR32_DMANXTDSC 0x310 /* DMA Next Descriptor Address */
139 #define AVR32_DMAADDRESS 0x314 /* DMA Channel Address */
190 * short_pkt = 0: transfer should be short terminated