Lines Matching +full:enforce +full:- +full:video +full:- +full:mode
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
255 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
256 * or the CMIC-SL (AKA ServerWorks GC_LE).
274 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
350 "firmware-assigned ranges fail to allocate during the initial device scan.");
363 "Transition from D3 -> D0 on resume.");
368 "Transition from D0 -> D3 on suspend.");
376 "Enable support for MSI-X interrupts");
381 "Rewrite entire MSI-X table when updating MSI-X entries");
385 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
400 "Ignore firmware-assigned resources for BARs.");
404 "Ignore firmware-assigned bus numbers.");
429 for (q = &pci_quirks[0]; q->devid; q++) { in pci_has_quirk()
430 if (q->devid == devid && q->type == quirk) in pci_has_quirk()
453 if ((dinfo->cfg.domain == domain) && in pci_find_dbsf()
454 (dinfo->cfg.bus == bus) && in pci_find_dbsf()
455 (dinfo->cfg.slot == slot) && in pci_find_dbsf()
456 (dinfo->cfg.func == func)) { in pci_find_dbsf()
461 return (dinfo != NULL ? dinfo->cfg.dev : NULL); in pci_find_dbsf()
472 if ((dinfo->cfg.vendor == vendor) && in pci_find_device()
473 (dinfo->cfg.device == device)) { in pci_find_device()
474 return (dinfo->cfg.dev); in pci_find_device()
487 if (dinfo->cfg.baseclass == class && in pci_find_class()
488 dinfo->cfg.subclass == subclass) { in pci_find_class()
489 return (dinfo->cfg.dev); in pci_find_class()
504 if (from != dinfo->cfg.dev) in pci_find_class_from()
509 if (dinfo->cfg.baseclass == class && in pci_find_class_from()
510 dinfo->cfg.subclass == subclass) { in pci_find_class_from()
511 return (dinfo->cfg.dev); in pci_find_class_from()
524 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, in pci_printf()
525 cfg->func); in pci_printf()
633 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) in pci_fixancient()
637 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) in pci_fixancient()
638 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; in pci_fixancient()
647 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_hdrtypedata()
649 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); in pci_hdrtypedata()
650 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); in pci_hdrtypedata()
651 cfg->mingnt = REG(PCIR_MINGNT, 1); in pci_hdrtypedata()
652 cfg->maxlat = REG(PCIR_MAXLAT, 1); in pci_hdrtypedata()
653 cfg->nummaps = PCI_MAXMAPS_0; in pci_hdrtypedata()
656 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); in pci_hdrtypedata()
657 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); in pci_hdrtypedata()
658 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); in pci_hdrtypedata()
659 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); in pci_hdrtypedata()
660 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); in pci_hdrtypedata()
661 cfg->nummaps = PCI_MAXMAPS_1; in pci_hdrtypedata()
664 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); in pci_hdrtypedata()
665 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); in pci_hdrtypedata()
666 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); in pci_hdrtypedata()
667 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); in pci_hdrtypedata()
668 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); in pci_hdrtypedata()
669 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); in pci_hdrtypedata()
670 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); in pci_hdrtypedata()
671 cfg->nummaps = PCI_MAXMAPS_2; in pci_hdrtypedata()
710 cfg = &devlist_entry->cfg; in pci_fill_devinfo()
712 cfg->domain = d; in pci_fill_devinfo()
713 cfg->bus = b; in pci_fill_devinfo()
714 cfg->slot = s; in pci_fill_devinfo()
715 cfg->func = f; in pci_fill_devinfo()
716 cfg->vendor = vid; in pci_fill_devinfo()
717 cfg->device = did; in pci_fill_devinfo()
718 cfg->cmdreg = REG(PCIR_COMMAND, 2); in pci_fill_devinfo()
719 cfg->statreg = REG(PCIR_STATUS, 2); in pci_fill_devinfo()
720 cfg->baseclass = REG(PCIR_CLASS, 1); in pci_fill_devinfo()
721 cfg->subclass = REG(PCIR_SUBCLASS, 1); in pci_fill_devinfo()
722 cfg->progif = REG(PCIR_PROGIF, 1); in pci_fill_devinfo()
723 cfg->revid = REG(PCIR_REVID, 1); in pci_fill_devinfo()
724 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); in pci_fill_devinfo()
725 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); in pci_fill_devinfo()
726 cfg->lattimer = REG(PCIR_LATTIMER, 1); in pci_fill_devinfo()
727 cfg->intpin = REG(PCIR_INTPIN, 1); in pci_fill_devinfo()
728 cfg->intline = REG(PCIR_INTLINE, 1); in pci_fill_devinfo()
730 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; in pci_fill_devinfo()
731 cfg->hdrtype &= ~PCIM_MFDEV; in pci_fill_devinfo()
732 STAILQ_INIT(&cfg->maps); in pci_fill_devinfo()
734 cfg->iov = NULL; in pci_fill_devinfo()
744 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; in pci_fill_devinfo()
745 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; in pci_fill_devinfo()
746 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; in pci_fill_devinfo()
747 devlist_entry->conf.pc_sel.pc_func = cfg->func; in pci_fill_devinfo()
748 devlist_entry->conf.pc_hdr = cfg->hdrtype; in pci_fill_devinfo()
750 devlist_entry->conf.pc_subvendor = cfg->subvendor; in pci_fill_devinfo()
751 devlist_entry->conf.pc_subdevice = cfg->subdevice; in pci_fill_devinfo()
752 devlist_entry->conf.pc_vendor = cfg->vendor; in pci_fill_devinfo()
753 devlist_entry->conf.pc_device = cfg->device; in pci_fill_devinfo()
755 devlist_entry->conf.pc_class = cfg->baseclass; in pci_fill_devinfo()
756 devlist_entry->conf.pc_subclass = cfg->subclass; in pci_fill_devinfo()
757 devlist_entry->conf.pc_progif = cfg->progif; in pci_fill_devinfo()
758 devlist_entry->conf.pc_revid = cfg->revid; in pci_fill_devinfo()
770 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ in pci_ea_fill_info()
771 cfg->ea.ea_location + (n), w) in pci_ea_fill_info()
781 if (cfg->ea.ea_location == 0) in pci_ea_fill_info()
784 STAILQ_INIT(&cfg->ea.ea_entries); in pci_ea_fill_info()
794 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) in pci_ea_fill_info()
799 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; in pci_ea_fill_info()
811 eae->eae_flags = val; in pci_ea_fill_info()
812 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; in pci_ea_fill_info()
827 eae->eae_base = base; in pci_ea_fill_info()
828 eae->eae_max_offset = max_offset; in pci_ea_fill_info()
830 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); in pci_ea_fill_info()
834 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, in pci_ea_fill_info()
835 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); in pci_ea_fill_info()
844 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) in pci_read_cap()
845 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) in pci_read_cap()
852 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_read_cap()
882 if (cfg->pp.pp_cap == 0) { in pci_read_cap()
883 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); in pci_read_cap()
884 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; in pci_read_cap()
885 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; in pci_read_cap()
886 if ((nextptr - ptr) > PCIR_POWER_DATA) in pci_read_cap()
887 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; in pci_read_cap()
891 /* Determine HT-specific capability type. */ in pci_read_cap()
895 cfg->ht.ht_slave = ptr; in pci_read_cap()
909 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", in pci_read_cap()
910 cfg->domain, cfg->bus, in pci_read_cap()
911 cfg->slot, cfg->func, in pci_read_cap()
916 cfg->ht.ht_msimap = ptr; in pci_read_cap()
917 cfg->ht.ht_msictrl = val; in pci_read_cap()
918 cfg->ht.ht_msiaddr = addr; in pci_read_cap()
924 cfg->msi.msi_location = ptr; in pci_read_cap()
925 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); in pci_read_cap()
926 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & in pci_read_cap()
929 case PCIY_MSIX: /* PCI MSI-X */ in pci_read_cap()
930 cfg->msix.msix_location = ptr; in pci_read_cap()
931 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); in pci_read_cap()
932 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & in pci_read_cap()
935 cfg->msix.msix_table_bar = PCIR_BAR(val & in pci_read_cap()
937 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; in pci_read_cap()
939 cfg->msix.msix_pba_bar = PCIR_BAR(val & in pci_read_cap()
941 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; in pci_read_cap()
944 cfg->vpd.vpd_reg = ptr; in pci_read_cap()
948 if ((cfg->hdrtype & PCIM_HDRTYPE) == in pci_read_cap()
951 cfg->subvendor = val & 0xffff; in pci_read_cap()
952 cfg->subdevice = val >> 16; in pci_read_cap()
955 case PCIY_PCIX: /* PCI-X */ in pci_read_cap()
957 * Assume we have a PCI-X chipset if we have in pci_read_cap()
958 * at least one PCI-PCI bridge with a PCI-X in pci_read_cap()
960 * PCI-express or HT chipsets might match on in pci_read_cap()
963 if ((cfg->hdrtype & PCIM_HDRTYPE) == in pci_read_cap()
966 cfg->pcix.pcix_location = ptr; in pci_read_cap()
968 case PCIY_EXPRESS: /* PCI-express */ in pci_read_cap()
970 * Assume we have a PCI-express chipset if we have in pci_read_cap()
971 * at least one PCI-express device. in pci_read_cap()
974 cfg->pcie.pcie_location = ptr; in pci_read_cap()
976 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; in pci_read_cap()
979 cfg->ea.ea_location = ptr; in pci_read_cap()
990 * slaves. PCI-PCI bridges have their windows enabled via in pci_read_cap()
993 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && in pci_read_cap()
994 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { in pci_read_cap()
997 cfg->domain, cfg->bus, cfg->slot, cfg->func); in pci_read_cap()
998 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; in pci_read_cap()
999 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, in pci_read_cap()
1019 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); in pci_read_vpd_reg()
1021 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { in pci_read_vpd_reg()
1022 if (--count < 0) in pci_read_vpd_reg()
1026 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); in pci_read_vpd_reg()
1039 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
1040 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
1041 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
1042 if (--count < 0)
1062 /* return 0 and one byte in *data if no read error, -1 else */
1069 if (vrs->bytesinval == 0) { in vpd_nextbyte()
1070 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) in vpd_nextbyte()
1071 return (-1); in vpd_nextbyte()
1072 vrs->val = le32toh(reg); in vpd_nextbyte()
1073 vrs->off += 4; in vpd_nextbyte()
1074 byte = vrs->val & 0xff; in vpd_nextbyte()
1075 vrs->bytesinval = 3; in vpd_nextbyte()
1077 vrs->val = vrs->val >> 8; in vpd_nextbyte()
1078 byte = vrs->val & 0xff; in vpd_nextbyte()
1079 vrs->bytesinval--; in vpd_nextbyte()
1082 vrs->cksum += byte; in vpd_nextbyte()
1087 /* return 0 on match, -1 and "unget" byte on no match */
1094 return (-1); in vpd_expectbyte()
1099 vrs->cksum -= data; in vpd_expectbyte()
1100 vrs->val = (vrs->val << 8) + data; in vpd_expectbyte()
1101 vrs->bytesinval++; in vpd_expectbyte()
1102 return (-1); in vpd_expectbyte()
1105 /* return size if tag matches, -1 on no match, -2 on read error */
1112 return (-1); in vpd_read_tag_size()
1118 return (-2); in vpd_read_tag_size()
1120 return (-2); in vpd_read_tag_size()
1141 /* read VPD keyword and return element size, return -1 on read error */
1148 return (-1); in vpd_read_elem_head()
1150 return (-1); in vpd_read_elem_head()
1152 return (-1); in vpd_read_elem_head()
1186 return (-1); in vpd_read_elem_data()
1202 vrs->cksum -= fixup; in vpd_fixup_cksum()
1205 /* fetch one read-only element and return size of heading + data */
1214 cfg = vrs->cfg; in next_vpd_ro_elem()
1215 vpd = &cfg->vpd; in next_vpd_ro_elem()
1218 return (-1); in next_vpd_ro_elem()
1219 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt); in next_vpd_ro_elem()
1220 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt]; in next_vpd_ro_elem()
1221 maxsize -= 3; in next_vpd_ro_elem()
1222 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize); in next_vpd_ro_elem()
1223 if (vpd_ros->value == NULL) in next_vpd_ro_elem()
1224 return (-1); in next_vpd_ro_elem()
1225 vpd_ros->len = len; in next_vpd_ro_elem()
1226 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') { in next_vpd_ro_elem()
1227 vpd_fixup_cksum(vrs, vpd_ros->value, len); in next_vpd_ro_elem()
1228 if (vrs->cksum != 0) { in next_vpd_ro_elem()
1230 "invalid VPD checksum %#hhx\n", vrs->cksum); in next_vpd_ro_elem()
1231 return (-1); in next_vpd_ro_elem()
1234 vpd->vpd_rocnt++; in next_vpd_ro_elem()
1248 cfg = vrs->cfg; in next_vpd_rw_elem()
1249 vpd = &cfg->vpd; in next_vpd_rw_elem()
1252 return (-1); in next_vpd_rw_elem()
1253 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt); in next_vpd_rw_elem()
1254 if (vpd->vpd_w == NULL) { in next_vpd_rw_elem()
1256 return (-1); in next_vpd_rw_elem()
1258 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt]; in next_vpd_rw_elem()
1259 maxsize -= 3; in next_vpd_rw_elem()
1260 vpd_w->start = vrs->off + 3 - vrs->bytesinval; in next_vpd_rw_elem()
1261 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize); in next_vpd_rw_elem()
1262 if (vpd_w->value == NULL) in next_vpd_rw_elem()
1263 return (-1); in next_vpd_rw_elem()
1264 vpd_w->len = len; in next_vpd_rw_elem()
1265 vpd->vpd_wcnt++; in next_vpd_rw_elem()
1276 free(vpd->vpd_ident, M_DEVBUF); in vpd_free()
1277 for (i = 0; i < vpd->vpd_rocnt; i++) in vpd_free()
1278 free(vpd->vpd_ros[i].value, M_DEVBUF); in vpd_free()
1279 free(vpd->vpd_ros, M_DEVBUF); in vpd_free()
1280 vpd->vpd_rocnt = 0; in vpd_free()
1281 for (i = 0; i < vpd->vpd_wcnt; i++) in vpd_free()
1282 free(vpd->vpd_w[i].value, M_DEVBUF); in vpd_free()
1283 free(vpd->vpd_w, M_DEVBUF); in vpd_free()
1284 vpd->vpd_wcnt = 0; in vpd_free()
1306 /* read VPD ident element - mandatory */ in pci_parse_vpd()
1312 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size); in pci_parse_vpd()
1313 if (cfg->vpd.vpd_ident == NULL) { in pci_parse_vpd()
1318 /* read VPD RO elements - mandatory */ in pci_parse_vpd()
1321 pci_printf(cfg, "no read-only VPD data found\n"); in pci_parse_vpd()
1327 pci_printf(cfg, "error accessing read-only VPD data\n"); in pci_parse_vpd()
1328 return (-1); in pci_parse_vpd()
1330 size -= elem_size; in pci_parse_vpd()
1334 return (-1); in pci_parse_vpd()
1336 /* read VPD RW elements - optional */ in pci_parse_vpd()
1338 if (size == -2) in pci_parse_vpd()
1339 return (-1); in pci_parse_vpd()
1344 return (-1); in pci_parse_vpd()
1346 size -= elem_size; in pci_parse_vpd()
1349 /* read empty END tag - mandatory */ in pci_parse_vpd()
1364 vpd_free(&cfg->vpd); in pci_read_vpd()
1365 cfg->vpd.vpd_cached = 1; in pci_read_vpd()
1374 pcicfgregs *cfg = &dinfo->cfg; in pci_get_vpd_ident_method()
1376 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_get_vpd_ident_method()
1379 *identptr = cfg->vpd.vpd_ident; in pci_get_vpd_ident_method()
1392 pcicfgregs *cfg = &dinfo->cfg; in pci_get_vpd_readonly_method()
1395 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_get_vpd_readonly_method()
1398 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) in pci_get_vpd_readonly_method()
1399 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, in pci_get_vpd_readonly_method()
1400 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { in pci_get_vpd_readonly_method()
1401 *vptr = cfg->vpd.vpd_ros[i].value; in pci_get_vpd_readonly_method()
1413 pcicfgregs *cfg = &dinfo->cfg; in pci_fetch_vpd_list()
1415 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_fetch_vpd_list()
1417 return (&cfg->vpd); in pci_fetch_vpd_list()
1511 pcicfgregs *cfg = &dinfo->cfg; in pci_find_cap_method()
1525 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_find_cap_method()
1591 pcicfgregs *cfg = &dinfo->cfg; in pci_find_extcap_method()
1595 /* Only supported for PCI-express devices. */ in pci_find_extcap_method()
1596 if (cfg->pcie.pcie_location == 0) in pci_find_extcap_method()
1628 pcicfgregs *cfg = &dinfo->cfg; in pci_find_next_extcap_method()
1632 /* Only supported for PCI-express devices. */ in pci_find_next_extcap_method()
1633 if (cfg->pcie.pcie_location == 0) in pci_find_next_extcap_method()
1654 * Support for MSI-X message interrupts.
1660 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_write_msix_entry()
1663 KASSERT(msix->msix_table_len > index, ("bogus index")); in pci_write_msix_entry()
1664 offset = msix->msix_table_offset + index * 16; in pci_write_msix_entry()
1665 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); in pci_write_msix_entry()
1666 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); in pci_write_msix_entry()
1667 bus_write_4(msix->msix_table_res, offset + 8, data); in pci_write_msix_entry()
1677 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_enable_msix_method()
1688 msix->msix_location + PCIR_MSIX_CTRL, in pci_enable_msix_method()
1689 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); in pci_enable_msix_method()
1694 /* Enable MSI -> HT mapping. */ in pci_enable_msix_method()
1702 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_mask_msix()
1705 KASSERT(msix->msix_msgnum > index, ("bogus index")); in pci_mask_msix()
1706 offset = msix->msix_table_offset + index * 16 + 12; in pci_mask_msix()
1707 val = bus_read_4(msix->msix_table_res, offset); in pci_mask_msix()
1714 bus_write_4(msix->msix_table_res, offset, val); in pci_mask_msix()
1721 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_unmask_msix()
1724 KASSERT(msix->msix_table_len > index, ("bogus index")); in pci_unmask_msix()
1725 offset = msix->msix_table_offset + index * 16 + 12; in pci_unmask_msix()
1726 val = bus_read_4(msix->msix_table_res, offset); in pci_unmask_msix()
1733 bus_write_4(msix->msix_table_res, offset, val); in pci_unmask_msix()
1740 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_pending_msix()
1743 KASSERT(msix->msix_table_len > index, ("bogus index")); in pci_pending_msix()
1744 offset = msix->msix_pba_offset + (index / 32) * 4; in pci_pending_msix()
1746 return (bus_read_4(msix->msix_pba_res, offset) & bit); in pci_pending_msix()
1750 * Restore MSI-X registers and table during resume. If MSI-X is
1751 * enabled then walk the virtual table to restore the actual MSI-X
1758 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_resume_msix()
1763 if (msix->msix_alloc > 0) { in pci_resume_msix()
1765 for (i = 0; i < msix->msix_msgnum; i++) in pci_resume_msix()
1769 for (i = 0; i < msix->msix_table_len; i++) { in pci_resume_msix()
1770 mte = &msix->msix_table[i]; in pci_resume_msix()
1771 if (mte->mte_vector == 0 || mte->mte_handlers == 0) in pci_resume_msix()
1773 mv = &msix->msix_vectors[mte->mte_vector - 1]; in pci_resume_msix()
1774 pci_write_msix_entry(dev, i, mv->mv_address, in pci_resume_msix()
1775 mv->mv_data); in pci_resume_msix()
1779 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, in pci_resume_msix()
1780 msix->msix_ctrl, 2); in pci_resume_msix()
1784 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1792 pcicfgregs *cfg = &dinfo->cfg; in pci_alloc_msix_method()
1801 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_alloc_msix_method()
1802 if (rle != NULL && rle->res != NULL) in pci_alloc_msix_method()
1806 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) in pci_alloc_msix_method()
1809 /* If MSI-X is blacklisted for this system, fail. */ in pci_alloc_msix_method()
1813 /* MSI-X capability present? */ in pci_alloc_msix_method()
1814 if (cfg->msix.msix_location == 0 || !pci_do_msix) in pci_alloc_msix_method()
1818 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, in pci_alloc_msix_method()
1819 cfg->msix.msix_table_bar); in pci_alloc_msix_method()
1820 if (rle == NULL || rle->res == NULL || in pci_alloc_msix_method()
1821 !(rman_get_flags(rle->res) & RF_ACTIVE)) in pci_alloc_msix_method()
1823 cfg->msix.msix_table_res = rle->res; in pci_alloc_msix_method()
1824 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { in pci_alloc_msix_method()
1825 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, in pci_alloc_msix_method()
1826 cfg->msix.msix_pba_bar); in pci_alloc_msix_method()
1827 if (rle == NULL || rle->res == NULL || in pci_alloc_msix_method()
1828 !(rman_get_flags(rle->res) & RF_ACTIVE)) in pci_alloc_msix_method()
1831 cfg->msix.msix_pba_res = rle->res; in pci_alloc_msix_method()
1835 "attempting to allocate %d MSI-X vectors (%d supported)\n", in pci_alloc_msix_method()
1836 *count, cfg->msix.msix_msgnum); in pci_alloc_msix_method()
1837 max = min(*count, cfg->msix.msix_msgnum); in pci_alloc_msix_method()
1846 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, in pci_alloc_msix_method()
1852 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); in pci_alloc_msix_method()
1854 device_printf(child, "using IRQ %ju for MSI-X\n", in pci_alloc_msix_method()
1855 rle->start); in pci_alloc_msix_method()
1864 device_printf(child, "using IRQs %ju", rle->start); in pci_alloc_msix_method()
1865 irq = rle->start; in pci_alloc_msix_method()
1868 rle = resource_list_find(&dinfo->resources, in pci_alloc_msix_method()
1872 if (rle->start == irq + 1) { in pci_alloc_msix_method()
1880 printf("-%d", irq); in pci_alloc_msix_method()
1885 printf(",%ju", rle->start); in pci_alloc_msix_method()
1886 irq = rle->start; in pci_alloc_msix_method()
1891 printf("-%d", irq); in pci_alloc_msix_method()
1892 printf(" for MSI-X\n"); in pci_alloc_msix_method()
1897 for (i = 0; i < cfg->msix.msix_msgnum; i++) in pci_alloc_msix_method()
1901 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, in pci_alloc_msix_method()
1903 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, in pci_alloc_msix_method()
1906 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_alloc_msix_method()
1907 cfg->msix.msix_vectors[i].mv_irq = rle->start; in pci_alloc_msix_method()
1908 cfg->msix.msix_table[i].mte_vector = i + 1; in pci_alloc_msix_method()
1911 /* Update control register to enable MSI-X. */ in pci_alloc_msix_method()
1912 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; in pci_alloc_msix_method()
1913 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, in pci_alloc_msix_method()
1914 cfg->msix.msix_ctrl, 2); in pci_alloc_msix_method()
1917 cfg->msix.msix_alloc = actual; in pci_alloc_msix_method()
1918 cfg->msix.msix_table_len = actual; in pci_alloc_msix_method()
1925 * resources consecutively to the first N messages in the MSI-X table.
1928 * populate the MSI-X table sparsely. This method allows the driver
1934 * maps directly to the MSI-X table in that index 0 in the array
1935 * specifies the vector for the first message in the MSI-X table, etc.
1942 * On successful return, each message with a non-zero vector will have
1948 * For example, suppose a driver has a MSI-X table with 6 messages and
1952 * have an MSI-X table of ABC--- (where - means no vector assigned).
1954 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1959 * at MSI-X table index X - 1 and will only be valid if a vector is
1967 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_remap_msix_method()
1973 * table can't be bigger than the actual MSI-X table in the in pci_remap_msix_method()
1976 if (count == 0 || count > msix->msix_msgnum) in pci_remap_msix_method()
1981 if (vectors[i] > msix->msix_alloc) in pci_remap_msix_method()
1989 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | in pci_remap_msix_method()
1993 used[vectors[i] - 1] = 1; in pci_remap_msix_method()
1994 for (i = 0; i < msix->msix_alloc - 1; i++) in pci_remap_msix_method()
2005 for (i = 0; i < msix->msix_table_len; i++) { in pci_remap_msix_method()
2006 if (msix->msix_table[i].mte_vector == 0) in pci_remap_msix_method()
2008 if (msix->msix_table[i].mte_handlers > 0) { in pci_remap_msix_method()
2012 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_remap_msix_method()
2014 if (rle->res != NULL) { in pci_remap_msix_method()
2021 for (i = 0; i < msix->msix_table_len; i++) { in pci_remap_msix_method()
2022 if (msix->msix_table[i].mte_vector == 0) in pci_remap_msix_method()
2024 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_remap_msix_method()
2031 free(msix->msix_table, M_DEVBUF); in pci_remap_msix_method()
2032 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, in pci_remap_msix_method()
2035 msix->msix_table[i].mte_vector = vectors[i]; in pci_remap_msix_method()
2036 msix->msix_table_len = count; in pci_remap_msix_method()
2039 j = msix->msix_alloc - 1; in pci_remap_msix_method()
2045 msix->msix_vectors[j].mv_irq); in pci_remap_msix_method()
2046 j--; in pci_remap_msix_method()
2050 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * in pci_remap_msix_method()
2052 free(msix->msix_vectors, M_DEVBUF); in pci_remap_msix_method()
2053 msix->msix_vectors = vec; in pci_remap_msix_method()
2054 msix->msix_alloc = j + 1; in pci_remap_msix_method()
2062 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; in pci_remap_msix_method()
2063 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, in pci_remap_msix_method()
2068 device_printf(child, "Remapped MSI-X IRQs as: "); in pci_remap_msix_method()
2073 printf("---"); in pci_remap_msix_method()
2076 msix->msix_vectors[vectors[i] - 1].mv_irq); in pci_remap_msix_method()
2088 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_release_msix()
2093 if (msix->msix_alloc == 0) in pci_release_msix()
2097 for (i = 0; i < msix->msix_table_len; i++) { in pci_release_msix()
2098 if (msix->msix_table[i].mte_vector == 0) in pci_release_msix()
2100 if (msix->msix_table[i].mte_handlers > 0) in pci_release_msix()
2102 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msix()
2104 if (rle->res != NULL) in pci_release_msix()
2108 /* Update control register to disable MSI-X. */ in pci_release_msix()
2109 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; in pci_release_msix()
2110 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, in pci_release_msix()
2111 msix->msix_ctrl, 2); in pci_release_msix()
2114 for (i = 0; i < msix->msix_table_len; i++) { in pci_release_msix()
2115 if (msix->msix_table[i].mte_vector == 0) in pci_release_msix()
2117 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msix()
2119 free(msix->msix_table, M_DEVBUF); in pci_release_msix()
2120 msix->msix_table_len = 0; in pci_release_msix()
2123 for (i = 0; i < msix->msix_alloc; i++) in pci_release_msix()
2125 msix->msix_vectors[i].mv_irq); in pci_release_msix()
2126 free(msix->msix_vectors, M_DEVBUF); in pci_release_msix()
2127 msix->msix_alloc = 0; in pci_release_msix()
2132 * Return the max supported MSI-X messages this device supports.
2141 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_count_method()
2143 if (pci_do_msix && msix->msix_location != 0) in pci_msix_count_method()
2144 return (msix->msix_msgnum); in pci_msix_count_method()
2152 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_pba_bar_method()
2154 if (pci_do_msix && msix->msix_location != 0) in pci_msix_pba_bar_method()
2155 return (msix->msix_pba_bar); in pci_msix_pba_bar_method()
2156 return (-1); in pci_msix_pba_bar_method()
2163 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_table_bar_method()
2165 if (pci_do_msix && msix->msix_location != 0) in pci_msix_table_bar_method()
2166 return (msix->msix_table_bar); in pci_msix_table_bar_method()
2167 return (-1); in pci_msix_table_bar_method()
2177 struct pcicfg_ht *ht = &dinfo->cfg.ht; in pci_ht_map_msi()
2179 if (!ht->ht_msimap) in pci_ht_map_msi()
2182 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && in pci_ht_map_msi()
2183 ht->ht_msiaddr >> 20 == addr >> 20) { in pci_ht_map_msi()
2184 /* Enable MSI -> HT mapping. */ in pci_ht_map_msi()
2185 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; in pci_ht_map_msi()
2186 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, in pci_ht_map_msi()
2187 ht->ht_msictrl, 2); in pci_ht_map_msi()
2190 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { in pci_ht_map_msi()
2191 /* Disable MSI -> HT mapping. */ in pci_ht_map_msi()
2192 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; in pci_ht_map_msi()
2193 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, in pci_ht_map_msi()
2194 ht->ht_msictrl, 2); in pci_ht_map_msi()
2205 cap = dinfo->cfg.pcie.pcie_location; in pci_get_relaxed_ordering_enabled()
2220 cap = dinfo->cfg.pcie.pcie_location; in pci_get_max_payload()
2236 cap = dinfo->cfg.pcie.pcie_location; in pci_get_max_read_req()
2252 cap = dinfo->cfg.pcie.pcie_location; in pci_set_max_read_req()
2259 size = (1 << (fls(size) - 1)); in pci_set_max_read_req()
2262 val |= (fls(size) - 8) << 12; in pci_set_max_read_req()
2273 cap = dinfo->cfg.pcie.pcie_location; in pcie_read_config()
2289 cap = dinfo->cfg.pcie.pcie_location; in pcie_write_config()
2296 * Adjusts a PCI-e capability register by clearing the bits in mask
2310 cap = dinfo->cfg.pcie.pcie_location; in pcie_adjust_config()
2332 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_enable_msi_method()
2335 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, in pci_enable_msi_method()
2337 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { in pci_enable_msi_method()
2338 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, in pci_enable_msi_method()
2340 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, in pci_enable_msi_method()
2343 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, in pci_enable_msi_method()
2347 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; in pci_enable_msi_method()
2348 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_enable_msi_method()
2349 msi->msi_ctrl, 2); in pci_enable_msi_method()
2351 /* Enable MSI -> HT mapping. */ in pci_enable_msi_method()
2359 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_disable_msi_method()
2361 /* Disable MSI -> HT mapping. */ in pci_disable_msi_method()
2365 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; in pci_disable_msi_method()
2366 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_disable_msi_method()
2367 msi->msi_ctrl, 2); in pci_disable_msi_method()
2379 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_resume_msi()
2383 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { in pci_resume_msi()
2384 address = msi->msi_addr; in pci_resume_msi()
2385 data = msi->msi_data; in pci_resume_msi()
2386 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, in pci_resume_msi()
2388 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { in pci_resume_msi()
2389 pci_write_config(dev, msi->msi_location + in pci_resume_msi()
2391 pci_write_config(dev, msi->msi_location + in pci_resume_msi()
2394 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, in pci_resume_msi()
2397 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, in pci_resume_msi()
2405 pcicfgregs *cfg = &dinfo->cfg; in pci_remap_intr_method()
2418 if (cfg->msi.msi_alloc > 0) { in pci_remap_intr_method()
2420 if (cfg->msi.msi_handlers == 0) in pci_remap_intr_method()
2422 for (i = 0; i < cfg->msi.msi_alloc; i++) { in pci_remap_intr_method()
2423 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, in pci_remap_intr_method()
2425 if (rle->start == irq) { in pci_remap_intr_method()
2431 dinfo->cfg.msi.msi_addr = addr; in pci_remap_intr_method()
2432 dinfo->cfg.msi.msi_data = data; in pci_remap_intr_method()
2441 * For MSI-X, we check to see if we have this IRQ. If we do, in pci_remap_intr_method()
2445 if (cfg->msix.msix_alloc > 0) { in pci_remap_intr_method()
2448 for (i = 0; i < cfg->msix.msix_alloc; i++) { in pci_remap_intr_method()
2449 mv = &cfg->msix.msix_vectors[i]; in pci_remap_intr_method()
2450 if (mv->mv_irq == irq) { in pci_remap_intr_method()
2455 mv->mv_address = addr; in pci_remap_intr_method()
2456 mv->mv_data = data; in pci_remap_intr_method()
2457 for (j = 0; j < cfg->msix.msix_table_len; j++) { in pci_remap_intr_method()
2458 mte = &cfg->msix.msix_table[j]; in pci_remap_intr_method()
2459 if (mte->mte_vector != i + 1) in pci_remap_intr_method()
2461 if (mte->mte_handlers == 0) in pci_remap_intr_method()
2493 * host-PCI bridge at device 0:0:0. In the future, it may become
2505 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ in pci_msi_blacklisted()
2527 * Returns true if the specified device is blacklisted because MSI-X
2529 * MSI-X doesn't either.
2545 * Determine if MSI-X is blacklisted globally on this system. If MSI
2546 * is blacklisted, assume that MSI-X is as well. Check for additional
2547 * chipsets where MSI works but MSI-X does not.
2574 pcicfgregs *cfg = &dinfo->cfg; in pci_alloc_msi_method()
2584 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_alloc_msi_method()
2585 if (rle != NULL && rle->res != NULL) in pci_alloc_msi_method()
2589 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) in pci_alloc_msi_method()
2597 if (cfg->msi.msi_location == 0 || !pci_do_msi) in pci_alloc_msi_method()
2603 *count, cfg->msi.msi_msgnum); in pci_alloc_msi_method()
2606 actual = min(*count, cfg->msi.msi_msgnum); in pci_alloc_msi_method()
2634 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, in pci_alloc_msi_method()
2652 if (irqs[i] == irqs[i - 1] + 1) { in pci_alloc_msi_method()
2659 printf("-%d", irqs[i - 1]); in pci_alloc_msi_method()
2669 printf("-%d", irqs[actual - 1]); in pci_alloc_msi_method()
2675 ctrl = cfg->msi.msi_ctrl; in pci_alloc_msi_method()
2677 ctrl |= (ffs(actual) - 1) << 4; in pci_alloc_msi_method()
2678 cfg->msi.msi_ctrl = ctrl; in pci_alloc_msi_method()
2679 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); in pci_alloc_msi_method()
2682 cfg->msi.msi_alloc = actual; in pci_alloc_msi_method()
2683 cfg->msi.msi_handlers = 0; in pci_alloc_msi_method()
2693 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_release_msi_method()
2697 /* Try MSI-X first. */ in pci_release_msi_method()
2703 if (msi->msi_alloc == 0) in pci_release_msi_method()
2705 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); in pci_release_msi_method()
2708 if (msi->msi_handlers > 0) in pci_release_msi_method()
2710 for (i = 0; i < msi->msi_alloc; i++) { in pci_release_msi_method()
2711 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msi_method()
2713 if (rle->res != NULL) in pci_release_msi_method()
2715 irqs[i] = rle->start; in pci_release_msi_method()
2719 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), in pci_release_msi_method()
2721 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; in pci_release_msi_method()
2722 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_release_msi_method()
2723 msi->msi_ctrl, 2); in pci_release_msi_method()
2726 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); in pci_release_msi_method()
2727 for (i = 0; i < msi->msi_alloc; i++) in pci_release_msi_method()
2728 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msi_method()
2731 msi->msi_alloc = 0; in pci_release_msi_method()
2732 msi->msi_addr = 0; in pci_release_msi_method()
2733 msi->msi_data = 0; in pci_release_msi_method()
2747 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_msi_count_method()
2749 if (pci_do_msi && msi->msi_location != 0) in pci_msi_count_method()
2750 return (msi->msi_msgnum); in pci_msi_count_method()
2764 if (dinfo->cfg.vpd.vpd_reg) in pci_freecfg()
2765 vpd_free(&dinfo->cfg.vpd); in pci_freecfg()
2767 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { in pci_freecfg()
2777 pci_numdevs--; in pci_freecfg()
2788 pcicfgregs *cfg = &dinfo->cfg; in pci_set_powerstate_method()
2792 if (cfg->pp.pp_cap == 0) in pci_set_powerstate_method()
2798 * behavior when going from D3 -> D3. in pci_set_powerstate_method()
2823 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) in pci_set_powerstate_method()
2830 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) in pci_set_powerstate_method()
2835 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) in pci_set_powerstate_method()
2850 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); in pci_set_powerstate_method()
2860 pcicfgregs *cfg = &dinfo->cfg; in pci_get_powerstate_method()
2864 if (cfg->pp.pp_cap != 0) { in pci_get_powerstate_method()
2865 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); in pci_get_powerstate_method()
2967 * New style pci driver. Parent device is either a pci-host-bridge or a
2968 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2976 pcicfgregs *cfg = &dinfo->cfg; in pci_print_verbose()
2978 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", in pci_print_verbose()
2979 cfg->vendor, cfg->device, cfg->revid); in pci_print_verbose()
2981 cfg->domain, cfg->bus, cfg->slot, cfg->func); in pci_print_verbose()
2982 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", in pci_print_verbose()
2983 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, in pci_print_verbose()
2984 cfg->mfdev); in pci_print_verbose()
2986 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); in pci_print_verbose()
2988 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, in pci_print_verbose()
2989 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); in pci_print_verbose()
2990 if (cfg->intpin > 0) in pci_print_verbose()
2992 cfg->intpin +'a' -1, cfg->intline); in pci_print_verbose()
2993 if (cfg->pp.pp_cap) { in pci_print_verbose()
2996 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); in pci_print_verbose()
2998 cfg->pp.pp_cap & PCIM_PCAP_SPEC, in pci_print_verbose()
2999 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", in pci_print_verbose()
3000 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", in pci_print_verbose()
3003 if (cfg->msi.msi_location) { in pci_print_verbose()
3006 ctrl = cfg->msi.msi_ctrl; in pci_print_verbose()
3008 cfg->msi.msi_msgnum, in pci_print_verbose()
3009 (cfg->msi.msi_msgnum == 1) ? "" : "s", in pci_print_verbose()
3013 if (cfg->msix.msix_location) { in pci_print_verbose()
3014 printf("\tMSI-X supports %d message%s ", in pci_print_verbose()
3015 cfg->msix.msix_msgnum, in pci_print_verbose()
3016 (cfg->msix.msix_msgnum == 1) ? "" : "s"); in pci_print_verbose()
3017 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) in pci_print_verbose()
3019 cfg->msix.msix_table_bar); in pci_print_verbose()
3022 cfg->msix.msix_table_bar, in pci_print_verbose()
3023 cfg->msix.msix_pba_bar); in pci_print_verbose()
3050 * The device ROM BAR is special. It is always a 32-bit in pci_read_bar()
3055 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { in pci_read_bar()
3088 * and combines the result into a 64-bit value." (section 6.2.5.1) in pci_read_bar()
3103 * the BAR of the low-level console device and when booting verbose, in pci_read_bar()
3123 /* The device ROM BAR is always a 32-bit memory BAR. */ in pci_write_bar()
3125 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) in pci_write_bar()
3128 ln2range = pci_maprange(pm->pm_value); in pci_write_bar()
3129 pci_write_config(dev, pm->pm_reg, base, 4); in pci_write_bar()
3131 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); in pci_write_bar()
3132 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); in pci_write_bar()
3134 pm->pm_value |= (pci_addr_t)pci_read_config(dev, in pci_write_bar()
3135 pm->pm_reg + 4, 4) << 32; in pci_write_bar()
3145 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { in pci_find_bar()
3146 if (pm->pm_reg == reg) in pci_find_bar()
3158 return (STAILQ_FIRST(&dinfo->cfg.maps)); in pci_first_bar()
3174 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && in pci_bar_enabled()
3175 !(pm->pm_value & PCIM_BIOS_ENABLE)) in pci_bar_enabled()
3178 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { in pci_bar_enabled()
3181 iov = dinfo->cfg.iov; in pci_bar_enabled()
3182 cmd = pci_read_config(iov->iov_pf, in pci_bar_enabled()
3183 iov->iov_pos + PCIR_SRIOV_CTL, 2); in pci_bar_enabled()
3188 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) in pci_bar_enabled()
3202 pm->pm_reg = reg; in pci_add_bar()
3203 pm->pm_value = value; in pci_add_bar()
3204 pm->pm_size = size; in pci_add_bar()
3205 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { in pci_add_bar()
3206 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", in pci_add_bar()
3209 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) in pci_add_bar()
3213 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); in pci_add_bar()
3215 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); in pci_add_bar()
3227 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { in pci_restore_bars()
3228 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) in pci_restore_bars()
3231 ln2range = pci_maprange(pm->pm_value); in pci_restore_bars()
3232 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); in pci_restore_bars()
3234 pci_write_config(dev, pm->pm_reg + 4, in pci_restore_bars()
3235 pm->pm_value >> 32, 4); in pci_restore_bars()
3260 maprange = pci_maprange(pm->pm_value); in pci_add_map()
3364 end = base + count - 1; in pci_add_map()
3414 * For ATA devices we need to decide early what addressing mode to use.
3418 * addressing mode.
3431 printf("Trying ATA native PCI addressing mode\n"); in pci_ata_maps()
3478 pcicfgregs *cfg = &dinfo->cfg; in pci_assign_interrupt()
3483 if (cfg->intpin == 0) in pci_assign_interrupt()
3490 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); in pci_assign_interrupt()
3502 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) in pci_assign_interrupt()
3505 irq = cfg->intline; in pci_assign_interrupt()
3513 if (irq != cfg->intline) { in pci_assign_interrupt()
3514 cfg->intline = irq; in pci_assign_interrupt()
3519 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); in pci_assign_interrupt()
3659 eec = -1; in xhci_early_takeover()
3710 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_reserve_secbus()
3775 count = end - start + 1; in pci_reserve_secbus()
3817 cfg = &dinfo->cfg; in pci_alloc_secbus()
3818 rl = &dinfo->resources; in pci_alloc_secbus()
3819 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_alloc_secbus()
3866 iov = dinfo->cfg.iov; in pci_ea_bei_to_rid()
3868 iov_pos = iov->iov_pos; in pci_ea_bei_to_rid()
3886 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + in pci_ea_bei_to_rid()
3890 return (-1); in pci_ea_bei_to_rid()
3901 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { in pci_ea_is_enabled()
3902 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) in pci_ea_is_enabled()
3903 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); in pci_ea_is_enabled()
3924 rl = &dinfo->resources; in pci_add_resources_ea()
3928 iov = dinfo->cfg.iov; in pci_add_resources_ea()
3931 if (dinfo->cfg.ea.ea_location == 0) in pci_add_resources_ea()
3934 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { in pci_add_resources_ea()
3936 * TODO: Ignore EA-BAR if is not enabled. in pci_add_resources_ea()
3941 * a legacy-BAR mechanism. in pci_add_resources_ea()
3943 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) in pci_add_resources_ea()
3946 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { in pci_add_resources_ea()
3965 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || in pci_add_resources_ea()
3966 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) in pci_add_resources_ea()
3973 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || in pci_add_resources_ea()
3974 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && in pci_add_resources_ea()
3975 (ea->eae_bei != PCIM_EA_BEI_ROM)) in pci_add_resources_ea()
3979 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); in pci_add_resources_ea()
3988 start = ea->eae_base; in pci_add_resources_ea()
3989 count = ea->eae_max_offset + 1; in pci_add_resources_ea()
3992 count = count * iov->iov_num_vfs; in pci_add_resources_ea()
3994 end = start + count - 1; in pci_add_resources_ea()
4009 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); in pci_add_resources_ea()
4011 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); in pci_add_resources_ea()
4017 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); in pci_add_resources_ea()
4038 cfg = &dinfo->cfg; in pci_add_resources()
4039 rl = &dinfo->resources; in pci_add_resources()
4040 devid = (cfg->device << 16) | cfg->vendor; in pci_add_resources()
4053 for (i = 0; i < cfg->nummaps;) { in pci_add_resources()
4065 for (q = &pci_quirks[0]; q->devid != 0; q++) in pci_add_resources()
4066 if (q->devid == devid && in pci_add_resources()
4067 q->type == PCI_QUIRK_UNMAP_REG && in pci_add_resources()
4068 q->arg1 == PCIR_BAR(i)) in pci_add_resources()
4070 if (q->devid != 0) { in pci_add_resources()
4081 for (q = &pci_quirks[0]; q->devid != 0; q++) in pci_add_resources()
4082 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) in pci_add_resources()
4083 pci_add_map(bus, dev, q->arg1, rl, force, 0); in pci_add_resources()
4085 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { in pci_add_resources()
4088 * Try to re-route interrupts. Sometimes the BIOS or in pci_add_resources()
4090 * If the re-route fails, then just stick with what we in pci_add_resources()
4150 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); in pci_add_children()
4289 vf_dinfo->cfg.flags |= PCICFG_VF; in pci_add_iov_child()
4292 return (vf_dinfo->cfg.dev); in pci_add_iov_child()
4314 if (dinfo->cfg.pcie.pcie_location == 0) in pcie_setup_mps()
4350 if (dinfo->cfg.pcie.pcie_location != 0 && in pci_add_child_clear_aer()
4351 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { in pci_add_child_clear_aer()
4352 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4356 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4363 pci_printf(&dinfo->cfg, in pci_add_child_clear_aer()
4364 "clearing AER UC 0x%08x -> 0x%08x\n", in pci_add_child_clear_aer()
4392 pci_printf(&dinfo->cfg, in pci_add_child_clear_aer()
4393 "clearing AER COR 0x%08x -> 0x%08x\n", in pci_add_child_clear_aer()
4409 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4413 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4423 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY); in pci_add_child()
4425 resource_list_init(&dinfo->resources); in pci_add_child()
4432 pci_child_added(dinfo->cfg.dev); in pci_add_child()
4437 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); in pci_add_child()
4467 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, in pci_attach_common()
4469 if (sc->sc_bus == NULL) { in pci_attach_common()
4476 sc->sc_dma_tag = bus_get_dma_tag(dev); in pci_attach_common()
4512 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); in pci_detach()
4597 * as MSI/MSI-X interrupts are never shared. in pci_suspend_child()
4599 rle = resource_list_find(&dinfo->resources, in pci_suspend_child()
4601 if (rle != NULL && rle->res != NULL) in pci_suspend_child()
4602 (void)bus_suspend_intr(child, rle->res); in pci_suspend_child()
4630 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_resume_child()
4631 if (rle != NULL && rle->res != NULL) in pci_resume_child()
4632 (void)bus_resume_intr(child, rle->res); in pci_resume_child()
4718 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); in pci_driver_added()
4755 * Check to see if the interrupt is MSI or MSI-X. in pci_setup_intr()
4762 if (dinfo->cfg.msi.msi_alloc > 0) { in pci_setup_intr()
4763 if (dinfo->cfg.msi.msi_addr == 0) { in pci_setup_intr()
4764 KASSERT(dinfo->cfg.msi.msi_handlers == 0, in pci_setup_intr()
4770 dinfo->cfg.msi.msi_addr = addr; in pci_setup_intr()
4771 dinfo->cfg.msi.msi_data = data; in pci_setup_intr()
4773 if (dinfo->cfg.msi.msi_handlers == 0) in pci_setup_intr()
4774 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, in pci_setup_intr()
4775 dinfo->cfg.msi.msi_data); in pci_setup_intr()
4776 dinfo->cfg.msi.msi_handlers++; in pci_setup_intr()
4778 KASSERT(dinfo->cfg.msix.msix_alloc > 0, in pci_setup_intr()
4779 ("No MSI or MSI-X interrupts allocated")); in pci_setup_intr()
4780 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, in pci_setup_intr()
4781 ("MSI-X index too high")); in pci_setup_intr()
4782 mte = &dinfo->cfg.msix.msix_table[rid - 1]; in pci_setup_intr()
4783 KASSERT(mte->mte_vector != 0, ("no message vector")); in pci_setup_intr()
4784 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; in pci_setup_intr()
4785 KASSERT(mv->mv_irq == rman_get_start(irq), in pci_setup_intr()
4787 if (mv->mv_address == 0) { in pci_setup_intr()
4788 KASSERT(mte->mte_handlers == 0, in pci_setup_intr()
4789 ("MSI-X table entry has handlers, but vector not mapped")); in pci_setup_intr()
4794 mv->mv_address = addr; in pci_setup_intr()
4795 mv->mv_data = data; in pci_setup_intr()
4805 mte->mte_handlers++; in pci_setup_intr()
4806 if (mte->mte_handlers == 1) { in pci_setup_intr()
4807 pci_enable_msix(child, rid - 1, mv->mv_address, in pci_setup_intr()
4808 mv->mv_data); in pci_setup_intr()
4809 pci_unmask_msix(child, rid - 1); in pci_setup_intr()
4814 * Make sure that INTx is disabled if we are using MSI/MSI-X, in pci_setup_intr()
4816 * in which case we "enable" INTx so MSI/MSI-X actually works. in pci_setup_intr()
4856 * Check to see if the interrupt is MSI or MSI-X. If so, in pci_teardown_intr()
4858 * MSI-X message, or disable MSI messages if the count in pci_teardown_intr()
4862 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); in pci_teardown_intr()
4863 if (rle->res != irq) in pci_teardown_intr()
4865 if (dinfo->cfg.msi.msi_alloc > 0) { in pci_teardown_intr()
4866 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, in pci_teardown_intr()
4867 ("MSI-X index too high")); in pci_teardown_intr()
4868 if (dinfo->cfg.msi.msi_handlers == 0) in pci_teardown_intr()
4870 dinfo->cfg.msi.msi_handlers--; in pci_teardown_intr()
4871 if (dinfo->cfg.msi.msi_handlers == 0) in pci_teardown_intr()
4874 KASSERT(dinfo->cfg.msix.msix_alloc > 0, in pci_teardown_intr()
4875 ("No MSI or MSI-X interrupts allocated")); in pci_teardown_intr()
4876 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, in pci_teardown_intr()
4877 ("MSI-X index too high")); in pci_teardown_intr()
4878 mte = &dinfo->cfg.msix.msix_table[rid - 1]; in pci_teardown_intr()
4879 if (mte->mte_handlers == 0) in pci_teardown_intr()
4881 mte->mte_handlers--; in pci_teardown_intr()
4882 if (mte->mte_handlers == 0) in pci_teardown_intr()
4883 pci_mask_msix(child, rid - 1); in pci_teardown_intr()
4889 ("%s: generic teardown failed for MSI/MSI-X", __func__)); in pci_teardown_intr()
4901 rl = &dinfo->resources; in pci_print_child()
4927 {PCIC_OLD, -1, 1, "old"},
4928 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"},
4929 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"},
4930 {PCIC_STORAGE, -1, 1, "mass storage"},
4940 {PCIC_NETWORK, -1, 1, "network"},
4946 {PCIC_DISPLAY, -1, 1, "display"},
4950 {PCIC_MULTIMEDIA, -1, 1, "multimedia"},
4951 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"},
4955 {PCIC_MEMORY, -1, 1, "memory"},
4958 {PCIC_BRIDGE, -1, 1, "bridge"},
4959 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"},
4960 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"},
4961 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"},
4962 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"},
4963 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"},
4964 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"},
4965 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"},
4966 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"},
4967 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"},
4968 {PCIC_SIMPLECOMM, -1, 1, "simple comms"},
4973 {PCIC_BASEPERIPH, -1, 0, "base peripheral"},
4978 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"},
4981 {PCIC_INPUTDEV, -1, 1, "input device"},
4987 {PCIC_DOCKING, -1, 1, "docking station"},
4988 {PCIC_PROCESSOR, -1, 1, "processor"},
4989 {PCIC_SERIALBUS, -1, 1, "serial bus"},
4996 {PCIC_WIRELESS, -1, 1, "wireless controller"},
5000 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"},
5002 {PCIC_SATCOM, -1, 1, "satellite communication"},
5007 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"},
5010 {PCIC_DASP, -1, 0, "dasp"},
5015 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"},
5042 if (pci_nomatch_tab[i].subclass == -1) { in pci_probe_nomatch()
5073 rl = &dinfo->resources; in pci_child_detached()
5081 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); in pci_child_detached()
5082 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { in pci_child_detached()
5083 if (dinfo->cfg.msi.msi_alloc != 0) in pci_child_detached()
5084 pci_printf(&dinfo->cfg, "Device leaked %d MSI " in pci_child_detached()
5085 "vectors\n", dinfo->cfg.msi.msi_alloc); in pci_child_detached()
5087 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " in pci_child_detached()
5088 "vectors\n", dinfo->cfg.msix.msix_alloc); in pci_child_detached()
5092 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); in pci_child_detached()
5094 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); in pci_child_detached()
5096 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); in pci_child_detached()
5114 * - devices cannot be listed without a corresponding VENDOR line.
5123 * is set to -1. Returns nonzero at the end of the database.
5135 *device = -1; in pci_describe_parse_line()
5136 *vendor = -1; in pci_describe_parse_line()
5139 left = pci_vendordata_size - (cp - pci_vendordata); in pci_describe_parse_line()
5157 left--; in pci_describe_parse_line()
5161 left--; in pci_describe_parse_line()
5167 left--; in pci_describe_parse_line()
5208 if (vendor != -1) { in pci_describe_device()
5235 cfg = &dinfo->cfg; in pci_read_ivar()
5246 *result = cfg->subvendor; in pci_read_ivar()
5249 *result = cfg->subdevice; in pci_read_ivar()
5252 *result = cfg->vendor; in pci_read_ivar()
5255 *result = cfg->device; in pci_read_ivar()
5258 *result = (cfg->device << 16) | cfg->vendor; in pci_read_ivar()
5261 *result = cfg->baseclass; in pci_read_ivar()
5264 *result = cfg->subclass; in pci_read_ivar()
5267 *result = cfg->progif; in pci_read_ivar()
5270 *result = cfg->revid; in pci_read_ivar()
5273 *result = cfg->intpin; in pci_read_ivar()
5276 *result = cfg->intline; in pci_read_ivar()
5279 *result = cfg->domain; in pci_read_ivar()
5282 *result = cfg->bus; in pci_read_ivar()
5285 *result = cfg->slot; in pci_read_ivar()
5288 *result = cfg->func; in pci_read_ivar()
5291 *result = cfg->cmdreg; in pci_read_ivar()
5294 *result = cfg->cachelnsz; in pci_read_ivar()
5297 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { in pci_read_ivar()
5298 *result = -1; in pci_read_ivar()
5301 *result = cfg->mingnt; in pci_read_ivar()
5304 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { in pci_read_ivar()
5305 *result = -1; in pci_read_ivar()
5308 *result = cfg->maxlat; in pci_read_ivar()
5311 *result = cfg->lattimer; in pci_read_ivar()
5328 dinfo->cfg.intpin = value; in pci_write_ivar()
5382 if (dinfo->cfg.dev) in DB_SHOW_COMMAND_FLAGS()
5383 name = device_get_name(dinfo->cfg.dev); in DB_SHOW_COMMAND_FLAGS()
5385 p = &dinfo->conf; in DB_SHOW_COMMAND_FLAGS()
5389 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : in DB_SHOW_COMMAND_FLAGS()
5391 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, in DB_SHOW_COMMAND_FLAGS()
5392 p->pc_sel.pc_func, (p->pc_class << 16) | in DB_SHOW_COMMAND_FLAGS()
5393 (p->pc_subclass << 8) | p->pc_progif, in DB_SHOW_COMMAND_FLAGS()
5394 (p->pc_subdevice << 16) | p->pc_subvendor, in DB_SHOW_COMMAND_FLAGS()
5395 (p->pc_device << 16) | p->pc_vendor, in DB_SHOW_COMMAND_FLAGS()
5396 p->pc_revid, p->pc_hdr); in DB_SHOW_COMMAND_FLAGS()
5407 struct resource_list *rl = &dinfo->resources; in pci_reserve_map()
5423 mapsize = pm->pm_size; in pci_reserve_map()
5424 map = pm->pm_value; in pci_reserve_map()
5429 * and unimplemented. Note: atapci in legacy mode are in pci_reserve_map()
5431 * have a atapci device in legacy mode and it fails in pci_reserve_map()
5440 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) in pci_reserve_map()
5449 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { in pci_reserve_map()
5530 rl = &dinfo->resources; in pci_alloc_multi_resource()
5531 cfg = &dinfo->cfg; in pci_alloc_multi_resource()
5541 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || in pci_alloc_multi_resource()
5542 cfg->msix.msix_alloc > 0)) in pci_alloc_multi_resource()
5550 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && in pci_alloc_multi_resource()
5551 (cfg->intpin != 0)) in pci_alloc_multi_resource()
5557 * PCI-PCI bridge I/O window resources are not BARs. in pci_alloc_multi_resource()
5561 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { in pci_alloc_multi_resource()
5601 if (dinfo->cfg.flags & PCICFG_VF) { in pci_alloc_resource()
5630 cfg = &dinfo->cfg; in pci_release_resource()
5633 if (cfg->flags & PCICFG_VF) { in pci_release_resource()
5647 * PCI-PCI bridge I/O window resources are not BARs. For in pci_release_resource()
5650 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && in pci_release_resource()
5661 rl = &dinfo->resources; in pci_release_resource()
5676 if (dinfo->cfg.flags & PCICFG_VF) { in pci_activate_resource()
5699 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) in pci_activate_resource()
5724 if (dinfo->cfg.flags & PCICFG_VF) { in pci_deactivate_resource()
5746 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) in pci_deactivate_resource()
5764 if (dinfo->cfg.flags & PCICFG_VF) { in pci_adjust_resource()
5793 if (dinfo->cfg.flags & PCICFG_VF) { in pci_map_resource()
5821 if (dinfo->cfg.flags & PCICFG_VF) { in pci_unmap_resource()
5845 rl = &dinfo->resources; in pci_child_deleted()
5859 if (rle->res) { in pci_child_deleted()
5860 if (rman_get_flags(rle->res) & RF_ACTIVE || in pci_child_deleted()
5861 resource_list_busy(rl, rle->type, rle->rid)) { in pci_child_deleted()
5862 pci_printf(&dinfo->cfg, in pci_child_deleted()
5865 rle->type, rle->rid, in pci_child_deleted()
5866 rman_get_start(rle->res)); in pci_child_deleted()
5867 bus_release_resource(child, rle->type, rle->rid, in pci_child_deleted()
5868 rle->res); in pci_child_deleted()
5870 resource_list_unreserve(rl, dev, child, rle->type, in pci_child_deleted()
5871 rle->rid); in pci_child_deleted()
5890 rl = &dinfo->resources; in pci_delete_resource()
5895 if (rle->res) { in pci_delete_resource()
5896 if (rman_get_flags(rle->res) & RF_ACTIVE || in pci_delete_resource()
5901 type, rid, rman_get_start(rle->res)); in pci_delete_resource()
5914 return (&dinfo->resources); in pci_get_resource_list()
5931 tag = sc->sc_dma_tag; in pci_get_dma_tag()
5941 return (sc->sc_dma_tag); in pci_get_dma_tag()
5949 pcicfgregs *cfg = &dinfo->cfg; in pci_read_config_method()
5953 * SR-IOV VFs don't implement the VID or DID registers, so we have to in pci_read_config_method()
5956 if (cfg->flags & PCICFG_VF) { in pci_read_config_method()
5960 return (cfg->device << 16 | cfg->vendor); in pci_read_config_method()
5962 return (cfg->vendor); in pci_read_config_method()
5964 return (cfg->vendor & 0xff); in pci_read_config_method()
5970 /* Note that an unaligned 4-byte read is an error. */ in pci_read_config_method()
5972 return (cfg->device); in pci_read_config_method()
5974 return (cfg->device & 0xff); in pci_read_config_method()
5983 cfg->bus, cfg->slot, cfg->func, reg, width)); in pci_read_config_method()
5991 pcicfgregs *cfg = &dinfo->cfg; in pci_write_config_method()
5994 cfg->bus, cfg->slot, cfg->func, reg, val, width); in pci_write_config_method()
6014 cfg = &dinfo->cfg; in pci_child_pnpinfo_method()
6016 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, in pci_child_pnpinfo_method()
6017 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, in pci_child_pnpinfo_method()
6018 cfg->progif); in pci_child_pnpinfo_method()
6044 pcicfgregs *cfg = &dinfo->cfg; in pci_assign_interrupt_method()
6047 cfg->intpin)); in pci_assign_interrupt_method()
6061 * Accept pciconf-style selectors of either pciD:B:S:F or in pci_lookup()
6133 cfg = &dinfo->cfg.pcie; in pci_cfg_restore_pcie()
6134 pos = cfg->pcie_location; in pci_cfg_restore_pcie()
6136 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; in pci_cfg_restore_pcie()
6138 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); in pci_cfg_restore_pcie()
6140 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6141 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || in pci_cfg_restore_pcie()
6142 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) in pci_cfg_restore_pcie()
6143 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); in pci_cfg_restore_pcie()
6145 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6146 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && in pci_cfg_restore_pcie()
6147 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) in pci_cfg_restore_pcie()
6148 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); in pci_cfg_restore_pcie()
6150 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6151 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) in pci_cfg_restore_pcie()
6152 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); in pci_cfg_restore_pcie()
6155 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); in pci_cfg_restore_pcie()
6156 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); in pci_cfg_restore_pcie()
6157 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); in pci_cfg_restore_pcie()
6165 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, in pci_cfg_restore_pcix()
6166 dinfo->cfg.pcix.pcix_command, 2); in pci_cfg_restore_pcix()
6174 * Restore the device to full power mode. We must do this in pci_cfg_restore()
6183 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); in pci_cfg_restore()
6184 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); in pci_cfg_restore()
6185 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); in pci_cfg_restore()
6186 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); in pci_cfg_restore()
6187 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); in pci_cfg_restore()
6188 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); in pci_cfg_restore()
6189 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { in pci_cfg_restore()
6191 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); in pci_cfg_restore()
6192 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); in pci_cfg_restore()
6196 dinfo->cfg.bridge.br_seclat, 1); in pci_cfg_restore()
6198 dinfo->cfg.bridge.br_subbus, 1); in pci_cfg_restore()
6200 dinfo->cfg.bridge.br_secbus, 1); in pci_cfg_restore()
6202 dinfo->cfg.bridge.br_pribus, 1); in pci_cfg_restore()
6204 dinfo->cfg.bridge.br_control, 2); in pci_cfg_restore()
6208 dinfo->cfg.bridge.br_seclat, 1); in pci_cfg_restore()
6210 dinfo->cfg.bridge.br_subbus, 1); in pci_cfg_restore()
6212 dinfo->cfg.bridge.br_secbus, 1); in pci_cfg_restore()
6214 dinfo->cfg.bridge.br_pribus, 1); in pci_cfg_restore()
6216 dinfo->cfg.bridge.br_control, 2); in pci_cfg_restore()
6221 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) in pci_cfg_restore()
6222 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); in pci_cfg_restore()
6225 * Restore extended capabilities for PCI-Express and PCI-X in pci_cfg_restore()
6227 if (dinfo->cfg.pcie.pcie_location != 0) in pci_cfg_restore()
6229 if (dinfo->cfg.pcix.pcix_location != 0) in pci_cfg_restore()
6232 /* Restore MSI and MSI-X configurations if they are present. */ in pci_cfg_restore()
6233 if (dinfo->cfg.msi.msi_location != 0) in pci_cfg_restore()
6235 if (dinfo->cfg.msix.msix_location != 0) in pci_cfg_restore()
6239 if (dinfo->cfg.iov != NULL) in pci_cfg_restore()
6251 cfg = &dinfo->cfg.pcie; in pci_cfg_save_pcie()
6252 pos = cfg->pcie_location; in pci_cfg_save_pcie()
6254 cfg->pcie_flags = RREG(PCIER_FLAGS); in pci_cfg_save_pcie()
6256 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; in pci_cfg_save_pcie()
6258 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); in pci_cfg_save_pcie()
6260 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6261 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || in pci_cfg_save_pcie()
6262 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) in pci_cfg_save_pcie()
6263 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); in pci_cfg_save_pcie()
6265 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6266 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && in pci_cfg_save_pcie()
6267 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) in pci_cfg_save_pcie()
6268 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); in pci_cfg_save_pcie()
6270 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6271 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) in pci_cfg_save_pcie()
6272 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); in pci_cfg_save_pcie()
6275 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); in pci_cfg_save_pcie()
6276 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); in pci_cfg_save_pcie()
6277 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); in pci_cfg_save_pcie()
6285 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, in pci_cfg_save_pcix()
6286 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); in pci_cfg_save_pcix()
6302 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); in pci_cfg_save()
6303 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); in pci_cfg_save()
6304 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); in pci_cfg_save()
6305 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); in pci_cfg_save()
6306 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); in pci_cfg_save()
6307 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); in pci_cfg_save()
6308 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); in pci_cfg_save()
6309 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); in pci_cfg_save()
6310 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); in pci_cfg_save()
6311 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); in pci_cfg_save()
6312 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); in pci_cfg_save()
6313 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { in pci_cfg_save()
6315 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); in pci_cfg_save()
6316 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); in pci_cfg_save()
6317 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); in pci_cfg_save()
6318 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); in pci_cfg_save()
6321 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, in pci_cfg_save()
6323 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, in pci_cfg_save()
6325 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, in pci_cfg_save()
6327 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, in pci_cfg_save()
6329 dinfo->cfg.bridge.br_control = pci_read_config(dev, in pci_cfg_save()
6333 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, in pci_cfg_save()
6335 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, in pci_cfg_save()
6337 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, in pci_cfg_save()
6339 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, in pci_cfg_save()
6341 dinfo->cfg.bridge.br_control = pci_read_config(dev, in pci_cfg_save()
6343 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); in pci_cfg_save()
6344 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); in pci_cfg_save()
6348 if (dinfo->cfg.pcie.pcie_location != 0) in pci_cfg_save()
6351 if (dinfo->cfg.pcix.pcix_location != 0) in pci_cfg_save()
6355 if (dinfo->cfg.iov != NULL) in pci_cfg_save()
6434 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); in pci_find_pcie_root_port()
6437 * Walk the bridge hierarchy until we find a PCI-e root in pci_find_pcie_root_port()
6438 * port or a non-PCI device. in pci_find_pcie_root_port()
6451 * PCI-PCI bridge. in pci_find_pcie_root_port()
6457 if (dinfo->cfg.pcie.pcie_location != 0 && in pci_find_pcie_root_port()
6458 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) in pci_find_pcie_root_port()
6466 * Wait for pending transactions to complete on a PCI-express function.
6472 * exceeded. If dev is not a PCI-express function, this returns true.
6481 cap = dinfo->cfg.pcie.pcie_location; in pcie_wait_for_pending_transactions()
6493 max_delay -= 100; in pcie_wait_for_pending_transactions()
6508 * For non-PCI-express functions this returns 0.
6516 cap = dinfo->cfg.pcie.pcie_location; in pcie_get_max_completion_timeout()
6525 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || in pcie_get_max_completion_timeout()
6565 s = "Uncorrectable (Non-Fatal)"; in pcie_apei_error()
6601 if (dinfo->cfg.pcie.pcie_location != 0) { in pcie_apei_error()
6602 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pcie_apei_error()
6607 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pcie_apei_error()
6622 * If dev is not a PCI-express function or does not support FLR, this
6627 * PCI-standard registers via pci_save_state() and
6638 cap = dinfo->cfg.pcie.pcie_location; in pcie_flr()
6649 * which will re-enable busmastering. in pcie_flr()
6658 pci_printf(&dinfo->cfg, in pcie_flr()
6663 * Extend the post-FLR delay to cover the maximum in pcie_flr()
6665 * during the FLR delay. Enforce a minimum delay of in pcie_flr()
6684 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); in pcie_flr()
6689 * Attempt a power-management reset by cycling the device in/out of D3
6789 while (nelt-- > 0) { in pci_match_device()
6791 if (id->match_flag_vendor) in pci_match_device()
6792 match &= vendor == id->vendor; in pci_match_device()
6793 if (id->match_flag_device) in pci_match_device()
6794 match &= device == id->device; in pci_match_device()
6795 if (id->match_flag_subvendor) in pci_match_device()
6796 match &= subvendor == id->subvendor; in pci_match_device()
6797 if (id->match_flag_subdevice) in pci_match_device()
6798 match &= subdevice == id->subdevice; in pci_match_device()
6799 if (id->match_flag_class) in pci_match_device()
6800 match &= class == id->class_id; in pci_match_device()
6801 if (id->match_flag_subclass) in pci_match_device()
6802 match &= subclass == id->subclass; in pci_match_device()
6803 if (id->match_flag_revid) in pci_match_device()
6804 match &= revid == id->revid; in pci_match_device()
6818 dev = dinfo->cfg.dev; in pci_print_faulted_dev_name()
6819 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, in pci_print_faulted_dev_name()
6820 dinfo->cfg.slot, dinfo->cfg.func); in pci_print_faulted_dev_name()
6836 dev = dinfo->cfg.dev; in pci_print_faulted_dev()
6845 if (dinfo->cfg.pcie.pcie_location != 0) { in pci_print_faulted_dev()
6847 dinfo->cfg.pcie.pcie_location + in pci_print_faulted_dev()
6855 dinfo->cfg.pcie.pcie_location + in pci_print_faulted_dev()
6899 dev = dinfo->cfg.dev; in db_clear_pcie_errors()
6900 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in db_clear_pcie_errors()
6902 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in db_clear_pcie_errors()
6922 dev = dinfo->cfg.dev; in DB_COMMAND_FLAGS()
6931 if (dinfo->cfg.pcie.pcie_location != 0) in DB_COMMAND_FLAGS()