Lines Matching +full:idle +full:- +full:wait +full:- +full:delay
1 /*-
47 {"w1-gpio", true},
56 #define OWC_GPIOBUS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
57 #define OWC_GPIOBUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
59 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
61 #define OWC_GPIOBUS_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
88 ofw_bus_search_compatible(dev, compat_data)->ocd_data)
92 device_set_desc(dev, "GPIO one-wire bus");
104 sc->sc_dev = dev;
107 /* Try to configure our pin from fdt data on fdt-based systems. */
109 &sc->sc_pin);
116 * on fdt-based systems).
120 err = gpio_pin_get_by_child_index(dev, OW_PIN, &sc->sc_pin);
124 device_printf(sc->sc_dev,
136 device_add_child(sc->sc_dev, "ow", DEVICE_UNIT_ANY);
151 gpio_pin_release(sc->sc_pin);
166 #define OUTPIN(sc) gpio_pin_setflags((sc)->sc_pin, GPIO_PIN_OUTPUT)
167 #define INPIN(sc) gpio_pin_setflags((sc)->sc_pin, GPIO_PIN_INPUT)
168 #define GETPIN(sc, bp) gpio_pin_is_active((sc)->sc_pin, (bp))
169 #define LOW(sc) gpio_pin_set_active((sc)->sc_pin, false)
172 * WRITE-ONE (see owll_if.m for timings) From Figure 4-1 AN-937
174 * |<---------tSLOT---->|<-tREC->|
179 * |<-tLOW1->| | |
180 * |<------15us--->| |
181 * |<--------60us---->|
195 DELAY(t->t_low1);
199 DELAY(t->t_slot - t->t_low1 + t->t_rec);
207 * WRITE-ZERO (see owll_if.m for timings) From Figure 4-2 AN-937
209 * |<---------tSLOT------>|<-tREC->|
214 * |<--15us->| | |
215 * |<------60us--->| |
216 * |<-------tLOW0------>|
230 DELAY(t->t_low0);
234 DELAY(t->t_slot - t->t_low0 + t->t_rec);
242 * READ-DATA (see owll_if.m for timings) From Figure 4-3 AN-937
244 * |<---------tSLOT------>|<-tREC->|
250 * |<------tRDV---->| |
251 * ->| |<-tRELEASE
253 * r -- allowed to pull high via the resitor when slave writes a 1-bit
271 DELAY(t->t_lowr);
282 } while (now - then < (t->t_rdv + 2) * SBT_1US && sample == false);
285 if (now - then < t->t_rdv * SBT_1US)
290 /* Wait out the rest of t_slot */
293 } while (now - then < (t->t_slot + t->t_rec) * SBT_1US);
299 * RESET AND PRESENCE PULSE (see owll_if.m for timings) From Figure 4-4 AN-937
301 * |<---------tRSTH------------>|
306 * |<----tRSTL--->| | |<-tPDL---->|
307 * | ->| |<-tR | |
314 * -1 = Bus wiring error (stuck low).
327 * Read the current state of the bus. The steady state of an idle bus is
335 *bit = -1;
344 DELAY(t->t_rstl);
346 /* Allow resistor to float line high and then wait for reset pulse */
348 DELAY(t->t_pdh + t->t_pdl / 2);
356 DELAY(t->t_rsth - (t->t_pdh + t->t_pdl / 2)); /* Timing not critical for this one */
365 *bit = -1;