Lines Matching +full:0 +full:x250

48 #define	NTB_HW_AMD_VENDOR_ID	0x1022
49 #define	NTB_HW_AMD_DEVICE_ID1	0x145B
50 #define	NTB_HW_AMD_DEVICE_ID2	0x148B
52 #define	NTB_HW_HYGON_VENDOR_ID	0x19D4
53 #define	NTB_HW_HYGON_DEVICE_ID1	0x145B
56 #define	NTB_DEF_PEER_IDX	0
61 #define	NTB_LIN_STA_ACTIVE_BIT	0x00000002
62 #define	NTB_LNK_STA_SPEED_MASK	0x000F0000
63 #define	NTB_LNK_STA_WIDTH_MASK	0x03F00000
87 #define QUIRK_MW0_32BIT	0x01
102 	NTB_CONFIG_BAR = 0,
150 	AMD_LINK_STATUS_OFFSET	= 0x68,
153 	AMD_CNTL_OFFSET		= 0x200,
162 	AMD_STA_OFFSET		= 0x204,
163 	AMD_PGSLV_OFFSET	= 0x208,
164 	AMD_SPAD_MUX_OFFSET	= 0x20C,
165 	AMD_SPAD_OFFSET		= 0x210,
166 	AMD_RSMU_HCID		= 0x250,
167 	AMD_RSMU_SIID		= 0x254,
168 	AMD_PSION_OFFSET	= 0x300,
169 	AMD_SSION_OFFSET	= 0x330,
170 	AMD_MMINDEX_OFFSET	= 0x400,
171 	AMD_MMDATA_OFFSET	= 0x404,
172 	AMD_SIDEINFO_OFFSET	= 0x408,
174 	AMD_SIDE_MASK		= BIT(0),
178 	AMD_ROMBARLMT_OFFSET	= 0x410,
179 	AMD_BAR1LMT_OFFSET	= 0x414,
180 	AMD_BAR23LMT_OFFSET	= 0x418,
181 	AMD_BAR45LMT_OFFSET	= 0x420,
184 	AMD_ROMBARXLAT_OFFSET	= 0x428,
185 	AMD_BAR1XLAT_OFFSET	= 0x430,
186 	AMD_BAR23XLAT_OFFSET	= 0x438,
187 	AMD_BAR45XLAT_OFFSET	= 0x440,
190 	AMD_DBFM_OFFSET		= 0x450,
191 	AMD_DBREQ_OFFSET	= 0x454,
192 	AMD_MIRRDBSTAT_OFFSET	= 0x458,
193 	AMD_DBMASK_OFFSET	= 0x45C,
194 	AMD_DBSTAT_OFFSET	= 0x460,
195 	AMD_INTMASK_OFFSET	= 0x470,
196 	AMD_INTSTAT_OFFSET	= 0x474,
199 	AMD_PEER_FLUSH_EVENT	= BIT(0),
211 	AMD_PMESTAT_OFFSET	= 0x480,
212 	AMD_PMSGTRIG_OFFSET	= 0x490,
213 	AMD_LTRLATENCY_OFFSET	= 0x494,
214 	AMD_FLUSHTRIG_OFFSET	= 0x498,
217 	AMD_SMUACK_OFFSET	= 0x4A0,
218 	AMD_SINRST_OFFSET	= 0x4A4,
219 	AMD_RSPNUM_OFFSET	= 0x4A8,
220 	AMD_SMU_SPADMUTEX	= 0x4B0,
221 	AMD_SMU_SPADOFFSET	= 0x4B4,
223 	AMD_PEER_OFFSET		= 0x400,