Lines Matching +full:1 +full:- +full:47
1 /*-
2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
4 * Copyright (c) 2015 - 2023 Intel Corporation
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
47 #define IRDMA_PE_DB_SIZE_4M 1
51 #define IRDMA_IRD_HW_SIZE_16 1
57 #define IRDMA_QP_STATE_IDLE 1
82 #define RDMA_READ_REQ_OPCODE 1
86 #define IRDMA_TERM_SENT 1
119 #define IRDMA_CQP_WAIT_POLL_REGS 1
144 #define IRDMA_TCP_STATE_CLOSED 1
163 #define IRDMA_CQ_TYPE_IWARP 1
181 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
184 #define IRDMAQP_TERM_SEND_TERM_ONLY 1
188 #define IRDMA_QP_TYPE_IWARP 1
196 #define IRDMA_CQE_QTYPE_SQ 1
201 #define IRDMA_QP_WQE_MIN_QUANTA 1
206 #define IRDMA_RQ_RSVD 1
209 #define IRDMA_FEATURE_CQ_RESIZE BIT_ULL(1)
228 IRDMA_OP_CEQ_DESTROY = 1,
273 IRDMA_OP_DELETE_LOCAL_MAC_ENTRY = 47,
333 #define GENMASK_ULL(high, low) ((0xFFFFFFFFFFFFFFFFULL >> (64ULL - ((high) - (low) + 1ULL))) << (lo…
336 #define GENMASK(high, low) ((0xFFFFFFFFUL >> (32UL - ((high) - (low) + 1UL))) << (low))
344 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
346 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
348 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
350 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
451 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)
458 #define IRDMA_CQPHC_DISABLE_PFPDUS_S 1
459 #define IRDMA_CQPHC_DISABLE_PFPDUS BIT_ULL(1)
471 #define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)
486 #define IRDMA_CQPHC_HW_MAJVER_GEN_2 1
551 #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)
642 #define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0)
689 #define IRDMA_CQPSQ_QP_CQNUMVALID_S 47
690 #define IRDMA_CQPSQ_QP_CQNUMVALID BIT_ULL(47)
728 #define IRDMA_CQPSQ_CQ_VIRTMAP_S 47
729 #define IRDMA_CQPSQ_CQ_VIRTMAP BIT_ULL(47)
761 #define IRDMA_CQPSQ_STAG_HPAGESIZE GENMASK_ULL(47, 46)
800 #define IRDMA_CQPSQ_MLM_MAC5 GENMASK_ULL(47, 40)
804 #define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0)
824 /* Manage Push Page - MPP */
838 /* Upload Context - UCTX */
867 #define IRDMA_CQPSQ_CEQ_VMAP_S 47
868 #define IRDMA_CQPSQ_CEQ_VMAP BIT_ULL(47)
879 #define IRDMA_CQPSQ_AEQ_VMAP_S 47
880 #define IRDMA_CQPSQ_AEQ_VMAP BIT_ULL(47)
900 #define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)
927 #define IRDMA_CQPSQ_UPESD_BM_CP_LM 1
955 #define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0)
997 #define IRDMAQPC_PMENA_S 47
998 #define IRDMAQPC_PMENA BIT_ULL(47)
1022 #define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)
1038 #define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)
1062 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
1209 #define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0)
1211 #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)
1268 #define IRDMAQPSQ_IMMDATAFLAG_S 47
1269 #define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47)
1310 #define IRDMAQPSQ_HPAGESIZE GENMASK_ULL(47, 46)
1361 #define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)
1373 (_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \
1378 (_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \
1383 (_ceq)->ceqe_base[_pos].buf \
1399 offset = IRDMA_GET_RING_OFFSET((_cq)->cq_ring, _i); \
1400 (_cqe) = (_cq)->cq_base[offset].buf; \
1404 (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
1409 ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
1427 (_ring).head = ((_ring).head + 1) % size; \
1430 (_retcode) = -ENOSPC; \
1441 (_retcode) = -ENOSPC; \
1449 (_ring).head = ((_ring).head + 1) % size; \
1452 (_retcode) = -ENOSPC; \
1459 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
1463 (_retcode) = -ENOSPC; \
1470 (_ring).tail = ((_ring).tail + 1) % (_ring).size
1473 (_ring).head = ((_ring).head + 1) % (_ring).size
1483 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \
1488 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \
1493 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \
1498 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \
1503 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \
1507 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \
1516 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1521 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
1526 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
1537 IRDMA_IWARP_PROTOCOL_ONLY = 1,
1568 enum { IRDMA_Q_ALIGNMENT_M = (128 - 1),
1569 IRDMA_AEQ_ALIGNMENT_M = (256 - 1),
1570 IRDMA_Q2_ALIGNMENT_M = (256 - 1),
1571 IRDMA_CEQ_ALIGNMENT_M = (256 - 1),
1572 IRDMA_CQ0_ALIGNMENT_M = (256 - 1),
1573 IRDMA_HOST_CTX_ALIGNMENT_M = (4 - 1),
1574 IRDMA_SHADOWAREA_M = (128 - 1),
1575 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M = (4 - 1),
1576 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),
1589 * set_64bit_val - set 64 bit value to hw wqe
1600 * set_32bit_val - set 32 bit value to hw wqe
1611 * get_64bit_val - read 64 bit value from wqe
1622 * get_32bit_val - read 32 bit value from wqe