60 	THIS_MACRO(GENI_FORCE_DEFAULT_REG,	0x020) \
61 	THIS_MACRO(GENI_OUTPUT_CTRL,		0x024) \
62 	THIS_MACRO(GENI_STATUS,			0x040) \
63 	THIS_MACRO(GENI_SER_M_CLK_CFG,		0x048) \
64 	THIS_MACRO(GENI_SER_S_CLK_CFG,		0x04c) \
65 	THIS_MACRO(GENI_IF_DISABLE_RO,		0x064) \
66 	THIS_MACRO(GENI_FW_REVISION_RO,		0x068) \
67 	THIS_MACRO(GENI_CLK_SEL,		0x07c) \
68 	THIS_MACRO(GENI_CFG_SEQ_START,		0x084) \
69 	THIS_MACRO(GENI_BYTE_GRANULARITY,	0x254) \
70 	THIS_MACRO(GENI_DMA_MODE_EN,		0x258) \
71 	THIS_MACRO(GENI_TX_PACKING_CFG0,	0x260) \
72 	THIS_MACRO(GENI_TX_PACKING_CFG1,	0x264) \
73 	THIS_MACRO(GENI_I2C_TX_TRANS_LEN,	0x26c) \
74 	THIS_MACRO(GENI_I2C_RX_TRANS_LEN,	0x270) \
75 	THIS_MACRO(GENI_I2C_SCL_COUNTERS,	0x278) \
76 	THIS_MACRO(GENI_RX_PACKING_CFG0,	0x284) \
77 	THIS_MACRO(GENI_RX_PACKING_CFG1,	0x288) \
78 	THIS_MACRO(GENI_M_CMD0,			0x600) \
79 	THIS_MACRO(GENI_M_CMD_CTRL_REG,		0x604) \
80 	THIS_MACRO(GENI_M_IRQ_STATUS,		0x610) \
81 	THIS_MACRO(GENI_M_IRQ_EN,		0x614) \
82 	THIS_MACRO(GENI_M_IRQ_CLEAR,		0x618) \
83 	THIS_MACRO(GENI_M_IRQ_EN_SET,		0x61c) \
84 	THIS_MACRO(GENI_M_IRQ_EN_CLEAR,		0x620) \
85 	THIS_MACRO(GENI_S_CMD0,			0x630) \
86 	THIS_MACRO(GENI_S_CMD_CTRL_REG,		0x634) \
87 	THIS_MACRO(GENI_S_IRQ_STATUS,		0x640) \
88 	THIS_MACRO(GENI_S_IRQ_EN,		0x644) \
89 	THIS_MACRO(GENI_S_IRQ_CLEAR,		0x648) \
90 	THIS_MACRO(GENI_S_IRQ_EN_SET,		0x64c) \
91 	THIS_MACRO(GENI_S_IRQ_EN_CLEAR,		0x650) \
92 	THIS_MACRO(GENI_TX_FIFOn,		0x700) \
93 	THIS_MACRO(GENI_RX_FIFOn,		0x780) \
94 	THIS_MACRO(GENI_TX_FIFO_STATUS,		0x800) \
95 	THIS_MACRO(GENI_RX_FIFO_STATUS,		0x804) \
96 	THIS_MACRO(GENI_TX_WATERMARK_REG,	0x80c) \
97 	THIS_MACRO(GENI_RX_WATERMARK_REG,	0x810) \
98 	THIS_MACRO(GENI_RX_RFR_WATERMARK_REG,	0x814) \
99 	THIS_MACRO(GENI_IOS,			0x908) \
100 	THIS_MACRO(GENI_M_GP_LENGTH,		0x910) \
101 	THIS_MACRO(GENI_S_GP_LENGTH,		0x914) \
102 	THIS_MACRO(GENI_DMA_TX_IRQ_STAT,	0xc40) \
103 	THIS_MACRO(GENI_DMA_TX_IRQ_CLR,		0xc44) \
104 	THIS_MACRO(GENI_DMA_TX_IRQ_EN,		0xc48) \
105 	THIS_MACRO(GENI_DMA_TX_IRQ_EN_CLR,	0xc4c) \
106 	THIS_MACRO(GENI_DMA_TX_IRQ_EN_SET,	0xc50) \
107 	THIS_MACRO(GENI_DMA_TX_FSM_RST,		0xc58) \
108 	THIS_MACRO(GENI_DMA_RX_IRQ_STAT,	0xd40) \
109 	THIS_MACRO(GENI_DMA_RX_IRQ_CLR,		0xd44) \
110 	THIS_MACRO(GENI_DMA_RX_IRQ_EN,		0xd48) \
111 	THIS_MACRO(GENI_DMA_RX_IRQ_EN_CLR,	0xd4c) \
112 	THIS_MACRO(GENI_DMA_RX_IRQ_EN_SET,	0xd50) \
113 	THIS_MACRO(GENI_DMA_RX_LEN_IN,		0xd54) \
114 	THIS_MACRO(GENI_DMA_RX_FSM_RST,		0xd58) \
115 	THIS_MACRO(GENI_IRQ_EN,			0xe1c) \
116 	THIS_MACRO(GENI_HW_PARAM_0,		0xe24) \
117 	THIS_MACRO(GENI_HW_PARAM_1,		0xe28)
140 static unsigned geniiic_debug_units = 0;
142 static SYSCTL_NODE(_hw, OID_AUTO, geniiic, CTLFLAG_RW, 0, "GENI I2C");
160 	if (sc->rx_buf != NULL && rx_fifo_status & 0x3f) {  in geniiic_intr()
163 		unsigned gotlen = (((rx_fifo_status & 0x3f) << 2)-1) * 4;  in geniiic_intr()
166 		// (Field is 3 bits, we'll only ever see 0…3)  in geniiic_intr()
167 		gotlen +=  (rx_fifo_status >> 28) & 0x7;  in geniiic_intr()
170 		for (cnt = 0; cnt < (rx_fifo_status & 0x3f); cnt++) {  in geniiic_intr()
173 			for (u = 0; u < 4 && sc->rx_len && gotlen; u++) {  in geniiic_intr()
174 				*sc->rx_buf++ = data & 0xff;  in geniiic_intr()
186 	if (m_status & (1<<0)) {  in geniiic_intr()
188 		WR(sc, GENI_M_IRQ_EN_CLEAR, (1<<0));  in geniiic_intr()
190 		WR(sc, GENI_M_IRQ_CLEAR, (1<<0));  in geniiic_intr()
200 		WR(sc, GENI_M_IRQ_EN, 0);  in geniiic_intr()
203 		    "Interrupt M_IRQ_STATUS 0x%x M_IRQ_EN 0x%x\n",  in geniiic_intr()
206 		    "Interrupt S_IRQ_STATUS 0x%x S_IRQ_EN 0x%x\n",  in geniiic_intr()
209 		    "Interrupt DMA_TX_IRQ_STAT 0x%x DMA_RX_IRQ_STAT 0x%x\n",  in geniiic_intr()
212 		    "Interrupt DMA_TX_IRQ_EN 0x%x DMA_RX_IRQ_EN 0x%x\n",  in geniiic_intr()
229 	for (timeout = 0; timeout < 10000; timeout++) {  in geniiic_wait_m_ireq()
232 			return (0);  in geniiic_wait_m_ireq()
255 	cmd = (0x2 << 27);  in geniiic_read()
267 	WR(sc, GENI_M_IRQ_EN, (1<<0) | (1<<26));  in geniiic_read()
277 	for (msec = 0; msec < 100; msec++) {  in geniiic_read()
279 		    "geniwait", SBT_1MS, SBT_1MS / 10, 0);  in geniiic_read()
294 		WR(sc, GENI_IRQ_EN, 0);  in geniiic_read()
301 	sc->rx_len = 0;  in geniiic_read()
307 	    "read " about " slave=0x%x len=0x%x, cmd=0x%x cmd_status=0x%x\n", \  in geniiic_read()
313 		if (unit < 32 && geniiic_debug_units & (1<<unit) && len == 0) {  in geniiic_read()
318 	if (len == 0)  in geniiic_read()
347 	cmd = (0x1 << 27);  in geniiic_write()
357 	for(timeout = 0; len > 0 && timeout < 100; timeout++) {  in geniiic_write()
360 			data = 0;  in geniiic_write()
361 			if (len) { data |= *buf <<  0; buf++; len--; }  in geniiic_write()
374 	if (len == 0 && error == 0)  in geniiic_write()
377 	    "write ERR len=%d, error=%d cmd=0x%x\n", len, error, cmd);  in geniiic_write()
387 	for (u = 0; u < nmsgs; u++) {  in geniiic_dumpmsg()
389 		    "  [%d] slave=0x%x, flags=0x%x len=0x%x buf=%p\n",  in geniiic_dumpmsg()
403 		pause_sbt("geniic_fail", SBT_1S * 5, SBT_1S, 0);  in geniiic_transfer()
416 	error = 0;  in geniiic_transfer()
417 	for (u = 0; u < nmsgs; u++) {  in geniiic_transfer()
434 		geniiic_reset(dev, 0, 0, NULL);  in geniiic_transfer()
439 		sc->nfail = 0;  in geniiic_transfer()
451 	WR(sc, GENI_M_IRQ_EN, 0);  in geniiic_reset()
452 	WR(sc, GENI_M_IRQ_CLEAR, ~0);  in geniiic_reset()
453 	WR(sc, GENI_DMA_TX_IRQ_EN_CLR, ~0);  in geniiic_reset()
454 	WR(sc, GENI_DMA_TX_IRQ_CLR, ~0);  in geniiic_reset()
455 	WR(sc, GENI_DMA_RX_IRQ_EN_CLR, ~0);  in geniiic_reset()
456 	WR(sc, GENI_DMA_RX_IRQ_CLR, ~0);  in geniiic_reset()
462 	for (u = 0; u < 1000; u++) {  in geniiic_reset()
463 		if (RD(sc, GENI_DMA_RX_IRQ_STAT) & 0x8)  in geniiic_reset()
467 	if (u > 0)  in geniiic_reset()
470 	for (u = 0; u < 1000; u++) {  in geniiic_reset()
471 		if (RD(sc, GENI_DMA_TX_IRQ_STAT) & 0x8)  in geniiic_reset()
475 	if (u > 0)  in geniiic_reset()
477 	return (0);  in geniiic_reset()
484 	int error = 0;  in geniiic_callback()
486 	return(0);  in geniiic_callback()
489 		if (sx_try_xlock(&sc->bus_lock) == 0)  in geniiic_callback()
514 	int error = 0;  in geniiic_attach()
522 	sc->rx_fifo_size = (RD(sc, GENI_HW_PARAM_1) >> 16) & 0x3f;  in geniiic_attach()
523 	device_printf(sc->dev, "  RX fifo size= 0x%x\n", sc->rx_fifo_size);  in geniiic_attach()
526 	//	GENI_BYTE_GRANULARITY	(0x00000000)  in geniiic_attach()
527 	//	GENI_TX_PACKING_CFG0	(0x0007f8fe)  in geniiic_attach()
529 	//	GENI_RX_PACKING_CFG0	(0x0007f8fe)  in geniiic_attach()
553 	int error = 0;  in geniiic_detach()
559 	WR(sc, GENI_M_IRQ_EN, 0);  in geniiic_detach()
568 	geniiic_reset(sc->dev, 0, 0, NULL);  in geniiic_detach()