Lines Matching +full:full +full:- +full:pwr +full:- +full:cycle
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
58 #define IGC_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
128 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
129 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
211 #define IGC_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
215 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
217 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
244 #define IGC_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */
279 /* 1000/H is not supported, nor spec-compliant. */
329 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
346 /* GPY211 - I225 defines */
507 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
605 /* Loop limit on how long we wait for auto-negotiation to complete */
623 #define IGC_TXCW_FD 0x00000020 /* TXCW full duplex */
627 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
842 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
844 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
846 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
852 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
854 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
864 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */
866 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
877 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */
879 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
881 /* 1000BASE-T Control Register */
897 /* 1000BASE-T Status Register */
920 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
921 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1005 #define IGC_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
1031 /* NVM Commands - Microwire */
1038 /* NVM Commands - SPI */
1042 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1070 /* PCI/PCI-X/PCI-EX Config space */
1096 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1129 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1140 * 1 = 50-80M
1141 * 2 = 80-110M
1142 * 3 = 110-140M
1171 * 15-5: page
1172 * 4-0: register offset
1190 /* Page 193 - Port Control Registers */
1193 #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */
1195 /* Page 194 - KMRN Registers */
1209 #define IGC_N0_QUEUE -1
1231 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1260 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1264 /* Minimum time for 100BASE-T where no data will be transmit following move out