Lines Matching +full:3 +full:- +full:ring
3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
9 * Copyright (c) 2000-2001 Network Security Technologies, Inc.
12 * Please send any comments, feedback, bug-fixes, or feature requests to
24 * 3. The name of the author may not be used to endorse or promote products
41 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
77 * The values below should multiple of 4 -- and be large enough to handle
81 * mac-key + rc4-key
200 #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
212 #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
213 #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
214 #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */
215 #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
230 #define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */
231 #define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */
232 #define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */
243 #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
244 #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
247 #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
248 #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
249 #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
250 #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
251 #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
252 #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
253 #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
256 #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
257 #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
258 #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
259 #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
260 #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
261 #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
262 #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
265 #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
266 #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
267 #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
268 #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
271 #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
272 #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
275 #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
276 #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
277 #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
278 #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
280 #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */
283 #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
284 #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
285 #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
286 #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
287 #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
288 #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
289 #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
290 #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
291 #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
292 #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
293 #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
294 #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
295 #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
296 #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
299 #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
300 #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
301 #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
302 #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
414 /* bits 5-9 reserved */
424 /* bits 14-15 reserved */
426 /* bits 17-31 reserved */
477 #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */