Lines Matching refs:mask_and_set
146 mask_and_set(struct pl061_softc *sc, long a, uint8_t m, uint8_t b) in mask_and_set() function
177 mask_and_set(sc, PL061_DIR, mask, flags & GPIO_PIN_OUTPUT ? mask : 0); in pl061_pin_setflags()
247 mask_and_set(sc, PL061_INTMASK, mask, 0); in pl061_pic_disable_intr()
265 mask_and_set(sc, PL061_INTMASK, mask, mask); in pl061_pic_enable_intr()
330 mask_and_set(sc, PL061_INTBOTHEDGES, mask, mask); in pl061_pic_setup_intr()
331 mask_and_set(sc, PL061_INTSENSE, mask, 0); in pl061_pic_setup_intr()
333 mask_and_set(sc, PL061_INTBOTHEDGES, mask, 0); in pl061_pic_setup_intr()
334 mask_and_set(sc, PL061_INTSENSE, mask, 0); in pl061_pic_setup_intr()
335 mask_and_set(sc, PL061_INTEVENT, mask, mask); in pl061_pic_setup_intr()
337 mask_and_set(sc, PL061_INTBOTHEDGES, mask, 0); in pl061_pic_setup_intr()
338 mask_and_set(sc, PL061_INTSENSE, mask, 0); in pl061_pic_setup_intr()
339 mask_and_set(sc, PL061_INTEVENT, mask, 0); in pl061_pic_setup_intr()
341 mask_and_set(sc, PL061_INTBOTHEDGES, mask, 0); in pl061_pic_setup_intr()
342 mask_and_set(sc, PL061_INTSENSE, mask, mask); in pl061_pic_setup_intr()
343 mask_and_set(sc, PL061_INTEVENT, mask, mask); in pl061_pic_setup_intr()
345 mask_and_set(sc, PL061_INTBOTHEDGES, mask, 0); in pl061_pic_setup_intr()
346 mask_and_set(sc, PL061_INTSENSE, mask, mask); in pl061_pic_setup_intr()
347 mask_and_set(sc, PL061_INTEVENT, mask, 0); in pl061_pic_setup_intr()
369 mask_and_set(sc, PL061_INTMASK, mask, 0); in pl061_pic_teardown_intr()