56 #define PCI_VENDOR_AMD			0x1022	/* AMD */
57 #define PCI_PRODUCT_AMD_GEODE_LX_CRYPTO	0x2082	/* Geode LX Crypto */
59 #define SB_GLD_MSR_CAP		0x58002000	/* RO - Capabilities */
60 #define SB_GLD_MSR_CONFIG	0x58002001	/* RW - Master Config */
61 #define SB_GLD_MSR_SMI		0x58002002	/* RW - SMI */
62 #define SB_GLD_MSR_ERROR	0x58002003	/* RW - Error */
63 #define SB_GLD_MSR_PM		0x58002004	/* RW - Power Mgmt */
64 #define SB_GLD_MSR_DIAG		0x58002005	/* RW - Diagnostic */
65 #define SB_GLD_MSR_CTRL		0x58002006	/* RW - Security Block Cntrl */
68 #define SB_GMC_DIV0		0x0000		/* AES update divisor values */
69 #define SB_GMC_DIV1		0x0001
70 #define SB_GMC_DIV2		0x0002
71 #define SB_GMC_DIV3		0x0003
72 #define SB_GMC_DIV_MASK		0x0003
73 #define SB_GMC_SBI		0x0004		/* AES swap bits */
74 #define SB_GMC_SBY		0x0008		/* AES swap bytes */
75 #define SB_GMC_TW		0x0010		/* Time write (EEPROM) */
76 #define SB_GMC_T_SEL0		0x0000		/* RNG post-proc: none */
77 #define SB_GMC_T_SEL1		0x0100		/* RNG post-proc: LFSR */
78 #define SB_GMC_T_SEL2		0x0200		/* RNG post-proc: whitener */
79 #define SB_GMC_T_SEL3		0x0300		/* RNG LFSR+whitener */
80 #define SB_GMC_T_SEL_MASK	0x0300
81 #define SB_GMC_T_NE		0x0400		/* Noise (generator) Enable */
82 #define SB_GMC_T_TM		0x0800		/* RNG test mode */
86 #define SB_CTL_A		0x0000		/* RW - SB Control A */
87 #define SB_CTL_B		0x0004		/* RW - SB Control B */
88 #define SB_AES_INT		0x0008		/* RW - SB AES Interrupt */
89 #define SB_SOURCE_A		0x0010		/* RW - Source A */
90 #define SB_DEST_A		0x0014		/* RW - Destination A */
91 #define SB_LENGTH_A		0x0018		/* RW - Length A */
92 #define SB_SOURCE_B		0x0020		/* RW - Source B */
93 #define SB_DEST_B		0x0024		/* RW - Destination B */
94 #define SB_LENGTH_B		0x0028		/* RW - Length B */
95 #define SB_WKEY			0x0030		/* WO - Writable Key 0-3 */
96 #define SB_WKEY_0		0x0030		/* WO - Writable Key 0 */
97 #define SB_WKEY_1		0x0034		/* WO - Writable Key 1 */
98 #define SB_WKEY_2		0x0038		/* WO - Writable Key 2 */
99 #define SB_WKEY_3		0x003C		/* WO - Writable Key 3 */
100 #define SB_CBC_IV		0x0040		/* RW - CBC IV 0-3 */
101 #define SB_CBC_IV_0		0x0040		/* RW - CBC IV 0 */
102 #define SB_CBC_IV_1		0x0044		/* RW - CBC IV 1 */
103 #define SB_CBC_IV_2		0x0048		/* RW - CBC IV 2 */
104 #define SB_CBC_IV_3		0x004C		/* RW - CBC IV 3 */
105 #define SB_RANDOM_NUM		0x0050		/* RW - Random Number */
106 #define SB_RANDOM_NUM_STATUS	0x0054		/* RW - Random Number Status */
107 #define SB_EEPROM_COMM		0x0800		/* RW - EEPROM Command */
108 #define SB_EEPROM_ADDR		0x0804		/* RW - EEPROM Address */
109 #define SB_EEPROM_DATA		0x0808		/* RW - EEPROM Data */
110 #define SB_EEPROM_SEC_STATE	0x080C		/* RW - EEPROM Security State */
113 #define SB_CTL_ST		0x0001		/* Start operation (enc/dec) */
114 #define SB_CTL_ENC		0x0002		/* Encrypt (0 is decrypt) */
115 #define SB_CTL_DEC		0x0000		/* Decrypt */
116 #define SB_CTL_WK		0x0004		/* Use writable key (we set) */
117 #define SB_CTL_DC		0x0008		/* Destination coherent */
118 #define SB_CTL_SC		0x0010		/* Source coherent */
119 #define SB_CTL_CBC		0x0020		/* CBC (0 is ECB) */
122 #define SB_AI_DISABLE_AES_A	0x0001		/* Disable AES A compl int */
123 #define SB_AI_ENABLE_AES_A	0x0000		/* Enable AES A compl int */
124 #define SB_AI_DISABLE_AES_B	0x0002		/* Disable AES B compl int */
125 #define SB_AI_ENABLE_AES_B	0x0000		/* Enable AES B compl int */
126 #define SB_AI_DISABLE_EEPROM	0x0004		/* Disable EEPROM op comp int */
127 #define SB_AI_ENABLE_EEPROM	0x0000		/* Enable EEPROM op compl int */
128 #define SB_AI_AES_A_COMPLETE   0x10000		/* AES A operation complete */
129 #define SB_AI_AES_B_COMPLETE   0x20000		/* AES B operation complete */
130 #define SB_AI_EEPROM_COMPLETE  0x40000		/* EEPROM operation complete */
137 #define SB_RNS_TRNG_VALID	0x0001		/* in SB_RANDOM_NUM_STATUS */
139 #define SB_MEM_SIZE		0x0810		/* Size of memory block */
141 #define SB_AES_ALIGN		0x0010		/* Source and dest buffers */
143 #define SB_AES_BLOCK_SIZE	0x0010
227 	{0,0}
236 DRIVER_MODULE(glxsb, pci, glxsb_driver, 0, 0);
263 	if ((msr & 0xFFFF00) != 0x130400) {  in glxsb_attach()
264 		device_printf(dev, "unknown ID 0x%x\n",  in glxsb_attach()
265 		    (int)((msr & 0xFFFF00) >> 16));  in glxsb_attach()
272 	sc->sc_rid = PCIR_BAR(0);  in glxsb_attach()
291 #if 0  in glxsb_attach()
300 	if (glxsb_dma_alloc(sc) != 0)  in glxsb_attach()
311 	    device_get_nameunit(dev)) != 0) {  in glxsb_attach()
315 	TASK_INIT(&sc->sc_cryptotask, 0, glxsb_crypto_task, sc);  in glxsb_attach()
318 	if (glxsb_crypto_setup(sc) != 0)  in glxsb_attach()
329 	return (0);  in glxsb_attach()
352 	return (0);  in glxsb_detach()
363 	*paddr = seg[0].ds_addr;  in glxsb_dmamap_cb()
377 				SB_AES_ALIGN, 0,	/* alignments, bounds */  in glxsb_dma_alloc()
387 	if (rc != 0) {  in glxsb_dma_alloc()
395 	if (rc != 0) {  in glxsb_dma_alloc()
404 	if (rc != 0) {  in glxsb_dma_alloc()
411 	return (0);  in glxsb_dma_alloc()
469 	if (sc->sc_cid < 0) {  in glxsb_crypto_setup()
476 	return (0);  in glxsb_crypto_setup()
483 	if (csp->csp_flags != 0)  in glxsb_crypto_probesession()
534 	if (csp->csp_auth_alg != 0) {  in glxsb_crypto_newsession()
536 		if (error != 0) {  in glxsb_crypto_newsession()
542 	return (0);  in glxsb_crypto_newsession()
561 	if (len & 0xF) {  in glxsb_aes()
611 	for (i = 0; i < GLXSB_MAX_AES_LEN * 10; i++) {  in glxsb_aes()
613 		if ((status & SB_CTL_ST) == 0)		/* Done */  in glxsb_aes()
614 			return (0);  in glxsb_aes()
634 	if ((crp->crp_payload_length % SB_AES_BLOCK_SIZE) != 0)  in glxsb_crypto_encdec()
658 	offset = 0;  in glxsb_crypto_encdec()
667 	while (tlen > 0) {  in glxsb_crypto_encdec()
678 		if (error != 0)  in glxsb_crypto_encdec()
701 	return (0);  in glxsb_crypto_encdec()
721 		if (error != 0)  in glxsb_crypto_task()
726 	if (error != 0)  in glxsb_crypto_task()
733 		if (error != 0)  in glxsb_crypto_task()
755 	if (sc->sc_task_count != 0) {  in glxsb_crypto_process()
766 	return(0);  in glxsb_crypto_process()