Lines Matching +full:1 +full:qav
10 1. Redistributions of source code must retain the above copyright notice,
193 /* QAV Tx mode control register */
196 /* QAV Tx mode control register bitfields masks */
197 /* QAV enable */
198 #define E1000_TQAVCTRL_MODE (1 << 0)
200 #define E1000_TQAVCTRL_FETCH_ARB (1 << 4)
202 #define E1000_TQAVCTRL_FETCH_TIMER_ENABLE (1 << 5)
204 #define E1000_TQAVCTRL_LAUNCH_ARB (1 << 8)
206 #define E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE (1 << 9)
208 #define E1000_TQAVCTRL_SP_WAIT_SR (1 << 10)
214 /* High credit registers where _n can be 0 or 1. */
221 /* QAV Tx mode control registers where _n can be 0 or 1. */
224 /* QAV Tx mode control register bitfields masks */
226 #define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */
227 #define E1000_TQAVCC_QUEUE_MODE (1U << 31) /* SP vs. SR Tx mode */
443 #define E1000_LSECTXPN1 0x0B01C /* Tx SA PN 1 - RW */
448 /* LinkSec Tx 128-bit Key 1 - WO */
503 #define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */
515 #define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */
537 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
635 #define E1000_ETQF_FILTER_ENABLE (1 << 26)
636 #define E1000_ETQF_IMM_INT (1 << 29)
637 #define E1000_ETQF_QUEUE_ENABLE (1U << 31)