Lines Matching +full:eee +full:- +full:pcs
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
262 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
264 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
341 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
342 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
344 /* Constants used to interpret the masked PCI-X bus speed. */
345 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
346 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
347 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
366 /* 1000/H is not supported, nor spec-compliant. */
421 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
728 /* Loop limit on how long we wait for auto-negotiation to complete */
752 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
862 /* I350 EEE defines */
863 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
864 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */
868 /* EEE status */
869 #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
872 #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */
875 #define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */
879 #define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */
880 #define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */
889 #define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
890 #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */
891 #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */
918 /* AFE CSR Offset for PCS CLK */
987 /* 1000BASE-T Control Register */
1003 /* 1000BASE-T Status Register */
1026 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1027 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1047 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1193 /* NVM Commands - Microwire */
1200 /* NVM Commands - SPI */
1204 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1232 /* PCI/PCI-X/PCI-EX Config space */
1256 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1307 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1318 * 1 = 50-80M
1319 * 2 = 80-110M
1320 * 3 = 110-140M
1383 * 15-5: page
1384 * 4-0: register offset
1402 /* Page 193 - Port Control Registers */
1407 /* Page 194 - KMRN Registers */
1451 /* Tx Rate-Scheduler Config fields */
1468 /* DMA Coalescing BMC-to-OS Watchdog Enable */