Lines Matching +full:phy +full:- +full:i2c
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
121 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
124 * Called to determine if the I2C pins are being used for I2C or as an
134 switch (hw->mac.type) { in e1000_sgmii_uses_mdio_82575()
155 * e1000_init_phy_params_82575 - Initialize PHY function ptrs
160 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82575() local
166 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic; in e1000_init_phy_params_82575()
167 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic; in e1000_init_phy_params_82575()
169 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82575()
170 phy->type = e1000_phy_none; in e1000_init_phy_params_82575()
174 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_82575()
175 phy->ops.power_down = e1000_power_down_phy_copper_base; in e1000_init_phy_params_82575()
177 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82575()
178 phy->reset_delay_us = 100; in e1000_init_phy_params_82575()
180 phy->ops.acquire = e1000_acquire_phy_base; in e1000_init_phy_params_82575()
181 phy->ops.check_reset_block = e1000_check_reset_block_generic; in e1000_init_phy_params_82575()
182 phy->ops.commit = e1000_phy_sw_reset_generic; in e1000_init_phy_params_82575()
183 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; in e1000_init_phy_params_82575()
184 phy->ops.release = e1000_release_phy_base; in e1000_init_phy_params_82575()
189 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; in e1000_init_phy_params_82575()
192 phy->ops.reset = e1000_phy_hw_reset_generic; in e1000_init_phy_params_82575()
200 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; in e1000_init_phy_params_82575()
201 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; in e1000_init_phy_params_82575()
203 switch (hw->mac.type) { in e1000_init_phy_params_82575()
207 phy->ops.read_reg = e1000_read_phy_reg_82580; in e1000_init_phy_params_82575()
208 phy->ops.write_reg = e1000_write_phy_reg_82580; in e1000_init_phy_params_82575()
212 phy->ops.read_reg = e1000_read_phy_reg_gs40g; in e1000_init_phy_params_82575()
213 phy->ops.write_reg = e1000_write_phy_reg_gs40g; in e1000_init_phy_params_82575()
216 phy->ops.read_reg = e1000_read_phy_reg_igp; in e1000_init_phy_params_82575()
217 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_82575()
221 /* Set phy->phy_addr and phy->id. */ in e1000_init_phy_params_82575()
224 /* Verify phy id and set remaining function pointers */ in e1000_init_phy_params_82575()
225 switch (phy->id) { in e1000_init_phy_params_82575()
231 phy->type = e1000_phy_m88; in e1000_init_phy_params_82575()
232 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_82575()
233 phy->ops.get_info = e1000_get_phy_info_m88; in e1000_init_phy_params_82575()
234 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; in e1000_init_phy_params_82575()
235 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; in e1000_init_phy_params_82575()
238 phy->type = e1000_phy_m88; in e1000_init_phy_params_82575()
239 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_82575()
240 phy->ops.get_info = e1000_get_phy_info_m88; in e1000_init_phy_params_82575()
241 phy->ops.get_cable_length = e1000_get_cable_length_m88; in e1000_init_phy_params_82575()
242 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; in e1000_init_phy_params_82575()
246 phy->type = e1000_phy_igp_3; in e1000_init_phy_params_82575()
247 phy->ops.check_polarity = e1000_check_polarity_igp; in e1000_init_phy_params_82575()
248 phy->ops.get_info = e1000_get_phy_info_igp; in e1000_init_phy_params_82575()
249 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; in e1000_init_phy_params_82575()
250 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; in e1000_init_phy_params_82575()
251 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; in e1000_init_phy_params_82575()
252 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; in e1000_init_phy_params_82575()
256 phy->type = e1000_phy_82580; in e1000_init_phy_params_82575()
257 phy->ops.check_polarity = e1000_check_polarity_82577; in e1000_init_phy_params_82575()
258 phy->ops.get_info = e1000_get_phy_info_82577; in e1000_init_phy_params_82575()
259 phy->ops.get_cable_length = e1000_get_cable_length_82577; in e1000_init_phy_params_82575()
260 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; in e1000_init_phy_params_82575()
261 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; in e1000_init_phy_params_82575()
262 phy->ops.force_speed_duplex = in e1000_init_phy_params_82575()
266 phy->type = e1000_phy_i210; in e1000_init_phy_params_82575()
267 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_82575()
268 phy->ops.get_info = e1000_get_phy_info_m88; in e1000_init_phy_params_82575()
269 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; in e1000_init_phy_params_82575()
270 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; in e1000_init_phy_params_82575()
271 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; in e1000_init_phy_params_82575()
272 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; in e1000_init_phy_params_82575()
275 ret_val = -E1000_ERR_PHY; in e1000_init_phy_params_82575()
279 /* Check if this PHY is configured for media swap. */ in e1000_init_phy_params_82575()
280 switch (phy->id) { in e1000_init_phy_params_82575()
285 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2); in e1000_init_phy_params_82575()
288 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1, in e1000_init_phy_params_82575()
297 hw->mac.ops.check_for_link = in e1000_init_phy_params_82575()
320 * e1000_init_mac_params_82575 - Init MAC func ptrs.
325 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_params_82575()
326 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in e1000_init_mac_params_82575()
336 mac->mta_reg_count = 128; in e1000_init_mac_params_82575()
338 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; in e1000_init_mac_params_82575()
340 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; in e1000_init_mac_params_82575()
341 if (mac->type == e1000_82576) in e1000_init_mac_params_82575()
342 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; in e1000_init_mac_params_82575()
343 if (mac->type == e1000_82580) in e1000_init_mac_params_82575()
344 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; in e1000_init_mac_params_82575()
345 if (mac->type == e1000_i350 || mac->type == e1000_i354) in e1000_init_mac_params_82575()
346 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; in e1000_init_mac_params_82575()
349 if (mac->type >= e1000_i350) in e1000_init_mac_params_82575()
350 dev_spec->eee_disable = false; in e1000_init_mac_params_82575()
353 if (mac->type >= e1000_i210) in e1000_init_mac_params_82575()
354 dev_spec->clear_semaphore_once = true; in e1000_init_mac_params_82575()
357 mac->asf_firmware_present = true; in e1000_init_mac_params_82575()
359 mac->has_fwsm = true; in e1000_init_mac_params_82575()
361 mac->arc_subsystem_valid = in e1000_init_mac_params_82575()
367 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; in e1000_init_mac_params_82575()
369 if (mac->type >= e1000_82580) in e1000_init_mac_params_82575()
370 mac->ops.reset_hw = e1000_reset_hw_82580; in e1000_init_mac_params_82575()
372 mac->ops.reset_hw = e1000_reset_hw_82575; in e1000_init_mac_params_82575()
374 if ((mac->type == e1000_i210) || (mac->type == e1000_i211)) in e1000_init_mac_params_82575()
375 mac->ops.init_hw = e1000_init_hw_i210; in e1000_init_mac_params_82575()
377 mac->ops.init_hw = e1000_init_hw_82575; in e1000_init_mac_params_82575()
379 mac->ops.setup_link = e1000_setup_link_generic; in e1000_init_mac_params_82575()
381 mac->ops.setup_physical_interface = in e1000_init_mac_params_82575()
382 (hw->phy.media_type == e1000_media_type_copper) in e1000_init_mac_params_82575()
385 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; in e1000_init_mac_params_82575()
387 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; in e1000_init_mac_params_82575()
389 mac->ops.check_for_link = e1000_check_for_link_82575; in e1000_init_mac_params_82575()
391 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; in e1000_init_mac_params_82575()
393 mac->ops.config_collision_dist = e1000_config_collision_dist_82575; in e1000_init_mac_params_82575()
395 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; in e1000_init_mac_params_82575()
396 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) { in e1000_init_mac_params_82575()
398 mac->ops.write_vfta = e1000_write_vfta_i350; in e1000_init_mac_params_82575()
400 mac->ops.clear_vfta = e1000_clear_vfta_i350; in e1000_init_mac_params_82575()
403 mac->ops.write_vfta = e1000_write_vfta_generic; in e1000_init_mac_params_82575()
405 mac->ops.clear_vfta = e1000_clear_vfta_generic; in e1000_init_mac_params_82575()
407 if (hw->mac.type >= e1000_82580) in e1000_init_mac_params_82575()
408 mac->ops.validate_mdi_setting = in e1000_init_mac_params_82575()
411 mac->ops.id_led_init = e1000_id_led_init_generic; in e1000_init_mac_params_82575()
413 mac->ops.blink_led = e1000_blink_led_generic; in e1000_init_mac_params_82575()
415 mac->ops.setup_led = e1000_setup_led_generic; in e1000_init_mac_params_82575()
417 mac->ops.cleanup_led = e1000_cleanup_led_generic; in e1000_init_mac_params_82575()
419 mac->ops.led_on = e1000_led_on_generic; in e1000_init_mac_params_82575()
420 mac->ops.led_off = e1000_led_off_generic; in e1000_init_mac_params_82575()
422 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; in e1000_init_mac_params_82575()
424 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; in e1000_init_mac_params_82575()
426 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync; in e1000_init_mac_params_82575()
428 mac->ops.release_swfw_sync = e1000_release_swfw_sync; in e1000_init_mac_params_82575()
430 /* set lan id for port to determine which phy lock to use */ in e1000_init_mac_params_82575()
431 hw->mac.ops.set_lan_id(hw); in e1000_init_mac_params_82575()
437 * e1000_init_nvm_params_82575 - Initialize NVM function ptrs
442 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_init_nvm_params_82575()
450 /* Added to a constant, "size" becomes the left-shift value in e1000_init_nvm_params_82575()
461 nvm->word_size = 1 << size; in e1000_init_nvm_params_82575()
462 if (hw->mac.type < e1000_i210) { in e1000_init_nvm_params_82575()
463 nvm->opcode_bits = 8; in e1000_init_nvm_params_82575()
464 nvm->delay_usec = 1; in e1000_init_nvm_params_82575()
466 switch (nvm->override) { in e1000_init_nvm_params_82575()
468 nvm->page_size = 32; in e1000_init_nvm_params_82575()
469 nvm->address_bits = 16; in e1000_init_nvm_params_82575()
472 nvm->page_size = 8; in e1000_init_nvm_params_82575()
473 nvm->address_bits = 8; in e1000_init_nvm_params_82575()
476 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; in e1000_init_nvm_params_82575()
477 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? in e1000_init_nvm_params_82575()
481 if (nvm->word_size == (1 << 15)) in e1000_init_nvm_params_82575()
482 nvm->page_size = 128; in e1000_init_nvm_params_82575()
484 nvm->type = e1000_nvm_eeprom_spi; in e1000_init_nvm_params_82575()
486 nvm->type = e1000_nvm_flash_hw; in e1000_init_nvm_params_82575()
490 nvm->ops.acquire = e1000_acquire_nvm_82575; in e1000_init_nvm_params_82575()
491 nvm->ops.release = e1000_release_nvm_82575; in e1000_init_nvm_params_82575()
492 if (nvm->word_size < (1 << 15)) in e1000_init_nvm_params_82575()
493 nvm->ops.read = e1000_read_nvm_eerd; in e1000_init_nvm_params_82575()
495 nvm->ops.read = e1000_read_nvm_spi; in e1000_init_nvm_params_82575()
497 nvm->ops.write = e1000_write_nvm_spi; in e1000_init_nvm_params_82575()
498 nvm->ops.validate = e1000_validate_nvm_checksum_generic; in e1000_init_nvm_params_82575()
499 nvm->ops.update = e1000_update_nvm_checksum_generic; in e1000_init_nvm_params_82575()
500 nvm->ops.valid_led_default = e1000_valid_led_default_82575; in e1000_init_nvm_params_82575()
503 switch (hw->mac.type) { in e1000_init_nvm_params_82575()
505 nvm->ops.validate = e1000_validate_nvm_checksum_82580; in e1000_init_nvm_params_82575()
506 nvm->ops.update = e1000_update_nvm_checksum_82580; in e1000_init_nvm_params_82575()
509 nvm->ops.validate = e1000_validate_nvm_checksum_i350; in e1000_init_nvm_params_82575()
510 nvm->ops.update = e1000_update_nvm_checksum_i350; in e1000_init_nvm_params_82575()
520 * e1000_init_function_pointers_82575 - Init func ptrs.
529 hw->mac.ops.init_params = e1000_init_mac_params_82575; in e1000_init_function_pointers_82575()
530 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; in e1000_init_function_pointers_82575()
531 hw->phy.ops.init_params = e1000_init_phy_params_82575; in e1000_init_function_pointers_82575()
532 hw->mbx.ops.init_params = e1000_init_mbx_params_pf; in e1000_init_function_pointers_82575()
536 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
541 * Reads the PHY register at offset using the serial gigabit media independent
547 s32 ret_val = -E1000_ERR_PARAM; in e1000_read_phy_reg_sgmii_82575()
552 DEBUGOUT1("PHY Address %u is out of range\n", offset); in e1000_read_phy_reg_sgmii_82575()
556 ret_val = hw->phy.ops.acquire(hw); in e1000_read_phy_reg_sgmii_82575()
562 hw->phy.ops.release(hw); in e1000_read_phy_reg_sgmii_82575()
569 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
574 * Writes the data to PHY register at the offset using the serial gigabit
580 s32 ret_val = -E1000_ERR_PARAM; in e1000_write_phy_reg_sgmii_82575()
585 DEBUGOUT1("PHY Address %d is out of range\n", offset); in e1000_write_phy_reg_sgmii_82575()
589 ret_val = hw->phy.ops.acquire(hw); in e1000_write_phy_reg_sgmii_82575()
595 hw->phy.ops.release(hw); in e1000_write_phy_reg_sgmii_82575()
602 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
605 * Retrieves the PHY address and ID for both PHY's which do and do not use
610 struct e1000_phy_info *phy = &hw->phy; in e1000_get_phy_id_82575() local
618 /* some i354 devices need an extra read for phy id */ in e1000_get_phy_id_82575()
619 if (hw->mac.type == e1000_i354) in e1000_get_phy_id_82575()
624 * we find one that works. For non-SGMII PHYs in e1000_get_phy_id_82575()
626 * work. The result of this function should mean phy->phy_addr in e1000_get_phy_id_82575()
627 * and phy->id are set correctly. in e1000_get_phy_id_82575()
630 phy->addr = 1; in e1000_get_phy_id_82575()
636 switch (hw->mac.type) { in e1000_get_phy_id_82575()
641 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; in e1000_get_phy_id_82575()
650 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; in e1000_get_phy_id_82575()
653 ret_val = -E1000_ERR_PHY; in e1000_get_phy_id_82575()
661 /* Power on sgmii phy if it is disabled */ in e1000_get_phy_id_82575()
670 * Therefore, we need to test 1-7 in e1000_get_phy_id_82575()
672 for (phy->addr = 1; phy->addr < 8; phy->addr++) { in e1000_get_phy_id_82575()
676 phy_id, phy->addr); in e1000_get_phy_id_82575()
679 * the only supported SGMII PHY product. in e1000_get_phy_id_82575()
684 DEBUGOUT1("PHY address %u was unreadable\n", in e1000_get_phy_id_82575()
685 phy->addr); in e1000_get_phy_id_82575()
689 /* A valid PHY type couldn't be found. */ in e1000_get_phy_id_82575()
690 if (phy->addr == 8) { in e1000_get_phy_id_82575()
691 phy->addr = 0; in e1000_get_phy_id_82575()
692 ret_val = -E1000_ERR_PHY; in e1000_get_phy_id_82575()
705 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
708 * Resets the PHY using the serial gigabit media independent interface.
713 struct e1000_phy_info *phy = &hw->phy; in e1000_phy_hw_reset_sgmii_82575() local
722 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); in e1000_phy_hw_reset_sgmii_82575()
724 if (!(hw->phy.ops.write_reg)) in e1000_phy_hw_reset_sgmii_82575()
731 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); in e1000_phy_hw_reset_sgmii_82575()
735 ret_val = hw->phy.ops.commit(hw); in e1000_phy_hw_reset_sgmii_82575()
739 if (phy->id == M88E1512_E_PHY_ID) in e1000_phy_hw_reset_sgmii_82575()
746 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
756 * PHY setup routines.
760 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d0_lplu_state_82575() local
766 if (!(hw->phy.ops.read_reg)) in e1000_set_d0_lplu_state_82575()
769 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); in e1000_set_d0_lplu_state_82575()
775 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82575()
781 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d0_lplu_state_82575()
784 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d0_lplu_state_82575()
790 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82575()
798 if (phy->smart_speed == e1000_smart_speed_on) { in e1000_set_d0_lplu_state_82575()
799 ret_val = phy->ops.read_reg(hw, in e1000_set_d0_lplu_state_82575()
806 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_82575()
811 } else if (phy->smart_speed == e1000_smart_speed_off) { in e1000_set_d0_lplu_state_82575()
812 ret_val = phy->ops.read_reg(hw, in e1000_set_d0_lplu_state_82575()
819 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_82575()
832 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
842 * PHY setup routines.
846 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d0_lplu_state_82580() local
867 if (phy->smart_speed == e1000_smart_speed_on) in e1000_set_d0_lplu_state_82580()
869 else if (phy->smart_speed == e1000_smart_speed_off) in e1000_set_d0_lplu_state_82580()
878 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
893 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d3_lplu_state_82580() local
908 if (phy->smart_speed == e1000_smart_speed_on) in e1000_set_d3_lplu_state_82580()
910 else if (phy->smart_speed == e1000_smart_speed_off) in e1000_set_d3_lplu_state_82580()
912 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || in e1000_set_d3_lplu_state_82580()
913 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || in e1000_set_d3_lplu_state_82580()
914 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { in e1000_set_d3_lplu_state_82580()
925 * e1000_acquire_nvm_82575 - Request for access to EEPROM
931 * EEPROM access and return -E1000_ERR_NVM (-1).
947 if (hw->mac.type == e1000_i350) { in e1000_acquire_nvm_82575()
958 if (hw->mac.type == e1000_82580) { in e1000_acquire_nvm_82575()
977 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
993 * e1000_get_cfg_done_82575 - Read config done bit
997 * completion status. NOTE: silicon which is EEPROM-less will fail trying
999 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1009 if (hw->bus.func == E1000_FUNC_1) in e1000_get_cfg_done_82575()
1011 else if (hw->bus.func == E1000_FUNC_2) in e1000_get_cfg_done_82575()
1013 else if (hw->bus.func == E1000_FUNC_3) in e1000_get_cfg_done_82575()
1019 timeout--; in e1000_get_cfg_done_82575()
1024 /* If EEPROM is not marked present, init the PHY manually */ in e1000_get_cfg_done_82575()
1026 (hw->phy.type == e1000_phy_igp_3)) in e1000_get_cfg_done_82575()
1033 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1049 if (hw->phy.media_type != e1000_media_type_copper) in e1000_get_link_up_info_82575()
1060 * e1000_check_for_link_82575 - Check for link
1073 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_check_for_link_82575()
1081 hw->mac.get_link_status = !hw->mac.serdes_has_link; in e1000_check_for_link_82575()
1084 * Configure Flow Control now that Auto-Neg has completed. in e1000_check_for_link_82575()
1086 * settings because we may have had to re-autoneg with a in e1000_check_for_link_82575()
1100 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1107 struct e1000_phy_info *phy = &hw->phy; in e1000_check_for_link_media_swap() local
1115 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in e1000_check_for_link_media_swap()
1119 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); in e1000_check_for_link_media_swap()
1127 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); in e1000_check_for_link_media_swap()
1131 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); in e1000_check_for_link_media_swap()
1139 if (port && (hw->dev_spec._82575.media_port != port)) { in e1000_check_for_link_media_swap()
1140 hw->dev_spec._82575.media_port = port; in e1000_check_for_link_media_swap()
1141 hw->dev_spec._82575.media_changed = true; in e1000_check_for_link_media_swap()
1146 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in e1000_check_for_link_media_swap()
1153 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in e1000_check_for_link_media_swap()
1162 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1171 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && in e1000_power_up_serdes_link_82575()
1191 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1196 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1202 struct e1000_mac_info *mac = &hw->mac; in e1000_get_pcs_speed_and_duplex_82575()
1209 * Read the PCS Status register for link state. For non-copper mode, in e1000_get_pcs_speed_and_duplex_82575()
1219 mac->serdes_has_link = true; in e1000_get_pcs_speed_and_duplex_82575()
1236 if (mac->type == e1000_i354) { in e1000_get_pcs_speed_and_duplex_82575()
1248 mac->serdes_has_link = false; in e1000_get_pcs_speed_and_duplex_82575()
1257 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1269 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && in e1000_shutdown_serdes_link_82575()
1293 * e1000_reset_hw_82575 - Reset hardware
1306 * Prevent the PCI-E bus from sticking if there is no TLP connection in e1000_reset_hw_82575()
1311 DEBUGOUT("PCI-E Master disable polling has failed.\n"); in e1000_reset_hw_82575()
1316 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); in e1000_reset_hw_82575()
1357 * e1000_init_hw_82575 - Initialize hardware
1364 struct e1000_mac_info *mac = &hw->mac; in e1000_init_hw_82575()
1370 ret_val = mac->ops.id_led_init(hw); in e1000_init_hw_82575()
1378 mac->ops.clear_vfta(hw); in e1000_init_hw_82575()
1383 hw->dev_spec._82575.mtu = 1500; in e1000_init_hw_82575()
1395 * e1000_setup_copper_link_82575 - Configure copper link settings
1398 * Configures the link for auto-neg or forced speed and duplex. Then we check
1416 switch (hw->mac.type) { in e1000_setup_copper_link_82575()
1434 /* allow time for SFP cage time to power up phy */ in e1000_setup_copper_link_82575()
1437 ret_val = hw->phy.ops.reset(hw); in e1000_setup_copper_link_82575()
1439 DEBUGOUT("Error resetting the PHY.\n"); in e1000_setup_copper_link_82575()
1443 switch (hw->phy.type) { in e1000_setup_copper_link_82575()
1447 switch (hw->phy.id) { in e1000_setup_copper_link_82575()
1473 ret_val = -E1000_ERR_PHY; in e1000_setup_copper_link_82575()
1486 * e1000_setup_serdes_link_82575 - Setup link for serdes
1489 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1492 * for auto-negotiation or forces speed/duplex.
1503 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && in e1000_setup_serdes_link_82575()
1524 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) in e1000_setup_serdes_link_82575()
1530 pcs_autoneg = hw->mac.autoneg; in e1000_setup_serdes_link_82575()
1534 /* sgmii mode lets the phy handle forcing speed/duplex */ in e1000_setup_serdes_link_82575()
1544 if (hw->mac.type == e1000_82575 || in e1000_setup_serdes_link_82575()
1545 hw->mac.type == e1000_82576) { in e1000_setup_serdes_link_82575()
1546 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); in e1000_setup_serdes_link_82575()
1557 * non-SGMII modes only supports a speed of 1000/Full for the in e1000_setup_serdes_link_82575()
1592 switch (hw->fc.requested_mode) { in e1000_setup_serdes_link_82575()
1627 * e1000_get_media_type_82575 - derives current media type.
1632 * - link mode set in the current port Init Control Word #3
1633 * - current link mode settings in CSR register
1634 * - MDIO vs. I2C PHY control interface chosen
1635 * - SFP module media type
1639 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in e1000_get_media_type_82575()
1644 /* Set internal phy as default */ in e1000_get_media_type_82575()
1645 dev_spec->sgmii_active = false; in e1000_get_media_type_82575()
1646 dev_spec->module_plugged = false; in e1000_get_media_type_82575()
1656 hw->phy.media_type = e1000_media_type_internal_serdes; in e1000_get_media_type_82575()
1659 hw->phy.media_type = e1000_media_type_copper; in e1000_get_media_type_82575()
1662 /* Get phy control interface type set (MDIO vs. I2C)*/ in e1000_get_media_type_82575()
1664 hw->phy.media_type = e1000_media_type_copper; in e1000_get_media_type_82575()
1665 dev_spec->sgmii_active = true; in e1000_get_media_type_82575()
1668 /* fall through for I2C based SGMII */ in e1000_get_media_type_82575()
1674 (hw->phy.media_type == e1000_media_type_unknown)) { in e1000_get_media_type_82575()
1679 hw->phy.media_type = e1000_media_type_internal_serdes; in e1000_get_media_type_82575()
1682 hw->phy.media_type = e1000_media_type_copper; in e1000_get_media_type_82575()
1683 dev_spec->sgmii_active = true; in e1000_get_media_type_82575()
1692 if (dev_spec->sgmii_active) in e1000_get_media_type_82575()
1709 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1719 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in e1000_set_sfp_media_type_82575()
1720 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags; in e1000_set_sfp_media_type_82575()
1724 /* Turn I2C interface ON and power on sfp cage */ in e1000_set_sfp_media_type_82575()
1739 timeout--; in e1000_set_sfp_media_type_82575()
1753 dev_spec->module_plugged = true; in e1000_set_sfp_media_type_82575()
1755 DEBUGOUT("PHY module is not SFP/SFF %x\n", tranceiver_type); in e1000_set_sfp_media_type_82575()
1757 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { in e1000_set_sfp_media_type_82575()
1758 hw->phy.media_type = e1000_media_type_internal_serdes; in e1000_set_sfp_media_type_82575()
1759 DEBUGOUT("PHY module is 1000_base_lxsx\n"); in e1000_set_sfp_media_type_82575()
1760 } else if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) { in e1000_set_sfp_media_type_82575()
1761 dev_spec->sgmii_active = true; in e1000_set_sfp_media_type_82575()
1762 hw->phy.media_type = e1000_media_type_internal_serdes; in e1000_set_sfp_media_type_82575()
1763 DEBUGOUT("PHY module is 100_base_fxlx\n"); in e1000_set_sfp_media_type_82575()
1764 } else if (eth_flags->e1000_base_t) { in e1000_set_sfp_media_type_82575()
1765 dev_spec->sgmii_active = true; in e1000_set_sfp_media_type_82575()
1766 hw->phy.media_type = e1000_media_type_copper; in e1000_set_sfp_media_type_82575()
1767 DEBUGOUT("PHY module is 1000_base_t\n"); in e1000_set_sfp_media_type_82575()
1769 hw->phy.media_type = e1000_media_type_unknown; in e1000_set_sfp_media_type_82575()
1770 DEBUGOUT("PHY module has not been recognized\n"); in e1000_set_sfp_media_type_82575()
1775 /* Restore I2C interface setting */ in e1000_set_sfp_media_type_82575()
1781 * e1000_valid_led_default_82575 - Verify a valid default LED config
1794 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); in e1000_valid_led_default_82575()
1801 switch (hw->phy.media_type) { in e1000_valid_led_default_82575()
1816 * e1000_sgmii_active_82575 - Return sgmii state
1825 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in e1000_sgmii_active_82575()
1826 return dev_spec->sgmii_active; in e1000_sgmii_active_82575()
1830 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1840 if (hw->mac.type == e1000_82575) { in e1000_reset_init_script_82575()
1868 * e1000_read_mac_addr_82575 - Read device MAC address
1893 * e1000_config_collision_dist_82575 - Configure collision distance
1915 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1974 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || in e1000_clear_hw_cntrs_82575()
1980 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
1985 * than the 10ms recommended by the pci-e spec. To address this we need to
2031 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2034 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2036 * enables/disables L2 switch anti-spoofing functionality.
2042 switch (hw->mac.type) { in e1000_vmdq_set_anti_spoofing_pf()
2058 /* The PF can spoof - it has to in order to in e1000_vmdq_set_anti_spoofing_pf()
2070 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2080 switch (hw->mac.type) { in e1000_vmdq_set_loopback_pf()
2107 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2126 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2131 * Reads the MDI control register in the PHY at offset and stores the
2140 ret_val = hw->phy.ops.acquire(hw); in e1000_read_phy_reg_82580()
2146 hw->phy.ops.release(hw); in e1000_read_phy_reg_82580()
2153 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2158 * Writes data to MDI control register in the PHY at offset.
2166 ret_val = hw->phy.ops.acquire(hw); in e1000_write_phy_reg_82580()
2172 hw->phy.ops.release(hw); in e1000_write_phy_reg_82580()
2179 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2194 if (hw->mac.type != e1000_82580) in e1000_reset_mdicnfg_82580()
2199 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + in e1000_reset_mdicnfg_82580()
2200 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, in e1000_reset_mdicnfg_82580()
2218 * e1000_reset_hw_82580 - Reset hardware
2230 bool global_device_reset = hw->dev_spec._82575.global_device_reset; in e1000_reset_hw_82580()
2234 hw->dev_spec._82575.global_device_reset = false; in e1000_reset_hw_82580()
2237 if (hw->mac.type == e1000_82580) in e1000_reset_hw_82580()
2244 * Prevent the PCI-E bus from sticking if there is no TLP connection in e1000_reset_hw_82580()
2249 DEBUGOUT("PCI-E Master disable polling has failed.\n"); in e1000_reset_hw_82580()
2260 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw, in e1000_reset_hw_82580()
2272 switch (hw->device_id) { in e1000_reset_hw_82580()
2309 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); in e1000_reset_hw_82580()
2315 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2335 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2352 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); in e1000_validate_nvm_checksum_with_offset()
2362 ret_val = -E1000_ERR_NVM; in e1000_validate_nvm_checksum_with_offset()
2371 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2389 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); in e1000_update_nvm_checksum_with_offset()
2396 checksum = (u16) NVM_SUM - checksum; in e1000_update_nvm_checksum_with_offset()
2397 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, in e1000_update_nvm_checksum_with_offset()
2407 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2423 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); in e1000_validate_nvm_checksum_82580()
2448 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2463 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); in e1000_update_nvm_checksum_82580()
2472 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, in e1000_update_nvm_checksum_82580()
2492 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2520 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2547 * __e1000_access_emi_reg - Read/write EMI register
2560 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); in __e1000_access_emi_reg()
2565 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); in __e1000_access_emi_reg()
2567 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); in __e1000_access_emi_reg()
2573 * e1000_read_emi_reg - Read Extended Management Interface register
2586 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2593 struct e1000_phy_info *phy = &hw->phy; in e1000_initialize_M88E1512_phy() local
2598 /* Check if this is correct PHY. */ in e1000_initialize_M88E1512_phy()
2599 if (phy->id != M88E1512_E_PHY_ID) in e1000_initialize_M88E1512_phy()
2602 /* Switch to PHY page 0xFF. */ in e1000_initialize_M88E1512_phy()
2603 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); in e1000_initialize_M88E1512_phy()
2607 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); in e1000_initialize_M88E1512_phy()
2611 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); in e1000_initialize_M88E1512_phy()
2615 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); in e1000_initialize_M88E1512_phy()
2619 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); in e1000_initialize_M88E1512_phy()
2623 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); in e1000_initialize_M88E1512_phy()
2627 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); in e1000_initialize_M88E1512_phy()
2631 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C); in e1000_initialize_M88E1512_phy()
2635 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); in e1000_initialize_M88E1512_phy()
2639 /* Switch to PHY page 0xFB. */ in e1000_initialize_M88E1512_phy()
2640 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); in e1000_initialize_M88E1512_phy()
2644 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D); in e1000_initialize_M88E1512_phy()
2648 /* Switch to PHY page 0x12. */ in e1000_initialize_M88E1512_phy()
2649 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); in e1000_initialize_M88E1512_phy()
2653 /* Change mode to SGMII-to-Copper */ in e1000_initialize_M88E1512_phy()
2654 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); in e1000_initialize_M88E1512_phy()
2658 /* Return the PHY to page 0. */ in e1000_initialize_M88E1512_phy()
2659 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); in e1000_initialize_M88E1512_phy()
2663 ret_val = phy->ops.commit(hw); in e1000_initialize_M88E1512_phy()
2665 DEBUGOUT("Error committing the PHY changes\n"); in e1000_initialize_M88E1512_phy()
2675 * e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2682 struct e1000_phy_info *phy = &hw->phy; in e1000_initialize_M88E1543_phy() local
2687 /* Check if this is correct PHY. */ in e1000_initialize_M88E1543_phy()
2688 if (phy->id != M88E1543_E_PHY_ID) in e1000_initialize_M88E1543_phy()
2691 /* Switch to PHY page 0xFF. */ in e1000_initialize_M88E1543_phy()
2692 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); in e1000_initialize_M88E1543_phy()
2696 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); in e1000_initialize_M88E1543_phy()
2700 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); in e1000_initialize_M88E1543_phy()
2704 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); in e1000_initialize_M88E1543_phy()
2708 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); in e1000_initialize_M88E1543_phy()
2712 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); in e1000_initialize_M88E1543_phy()
2716 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); in e1000_initialize_M88E1543_phy()
2720 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C); in e1000_initialize_M88E1543_phy()
2724 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); in e1000_initialize_M88E1543_phy()
2728 /* Switch to PHY page 0xFB. */ in e1000_initialize_M88E1543_phy()
2729 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); in e1000_initialize_M88E1543_phy()
2733 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D); in e1000_initialize_M88E1543_phy()
2737 /* Switch to PHY page 0x12. */ in e1000_initialize_M88E1543_phy()
2738 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); in e1000_initialize_M88E1543_phy()
2742 /* Change mode to SGMII-to-Copper */ in e1000_initialize_M88E1543_phy()
2743 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); in e1000_initialize_M88E1543_phy()
2747 /* Switch to PHY page 1. */ in e1000_initialize_M88E1543_phy()
2748 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1); in e1000_initialize_M88E1543_phy()
2752 /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */ in e1000_initialize_M88E1543_phy()
2753 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140); in e1000_initialize_M88E1543_phy()
2757 /* Return the PHY to page 0. */ in e1000_initialize_M88E1543_phy()
2758 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); in e1000_initialize_M88E1543_phy()
2762 ret_val = phy->ops.commit(hw); in e1000_initialize_M88E1543_phy()
2764 DEBUGOUT("Error committing the PHY changes\n"); in e1000_initialize_M88E1543_phy()
2774 * e1000_set_eee_i350 - Enable/disable EEE support
2788 if ((hw->mac.type < e1000_i350) || in e1000_set_eee_i350()
2789 (hw->phy.media_type != e1000_media_type_copper)) in e1000_set_eee_i350()
2795 if (!(hw->dev_spec._82575.eee_disable)) { in e1000_set_eee_i350()
2829 * e1000_set_eee_i354 - Enable/disable EEE support
2839 struct e1000_phy_info *phy = &hw->phy; in e1000_set_eee_i354() local
2845 if ((hw->phy.media_type != e1000_media_type_copper) || in e1000_set_eee_i354()
2846 ((phy->id != M88E1543_E_PHY_ID) && in e1000_set_eee_i354()
2847 (phy->id != M88E1512_E_PHY_ID))) in e1000_set_eee_i354()
2850 if (!hw->dev_spec._82575.eee_disable) { in e1000_set_eee_i354()
2851 /* Switch to PHY page 18. */ in e1000_set_eee_i354()
2852 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); in e1000_set_eee_i354()
2856 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, in e1000_set_eee_i354()
2862 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, in e1000_set_eee_i354()
2867 /* Return the PHY to page 0. */ in e1000_set_eee_i354()
2868 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); in e1000_set_eee_i354()
2912 * e1000_get_eee_status_i354 - Get EEE status
2921 struct e1000_phy_info *phy = &hw->phy; in e1000_get_eee_status_i354() local
2928 if ((hw->phy.media_type != e1000_media_type_copper) || in e1000_get_eee_status_i354()
2929 ((phy->id != M88E1543_E_PHY_ID) && in e1000_get_eee_status_i354()
2930 (phy->id != M88E1512_E_PHY_ID))) in e1000_get_eee_status_i354()
2952 * e1000_clear_vfta_i350 - Clear VLAN filter table
2974 * e1000_write_vfta_i350 - Write value to VLAN filter table
2996 * e1000_set_i2c_bb - Enable I2C bit-bang
2999 * Enable I2C bit-bang interface
3025 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3031 * Performs byte read operation over I2C interface at
3049 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) in e1000_read_i2c_byte_generic()
3095 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in e1000_read_i2c_byte_generic()
3100 DEBUGOUT("I2C byte read error - Retrying.\n"); in e1000_read_i2c_byte_generic()
3102 DEBUGOUT("I2C byte read error.\n"); in e1000_read_i2c_byte_generic()
3106 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in e1000_read_i2c_byte_generic()
3114 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3120 * Performs byte write operation over I2C interface at
3135 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) { in e1000_write_i2c_byte_generic()
3174 DEBUGOUT("I2C byte write error - Retrying.\n"); in e1000_write_i2c_byte_generic()
3176 DEBUGOUT("I2C byte write error.\n"); in e1000_write_i2c_byte_generic()
3179 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in e1000_write_i2c_byte_generic()
3187 * e1000_i2c_start - Sets I2C start condition
3190 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3218 * e1000_i2c_stop - Sets I2C stop condition
3221 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3243 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3247 * Clocks in one byte data via I2C data/clock
3257 for (i = 7; i >= 0; i--) { in e1000_clock_in_i2c_byte()
3264 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3268 * Clocks out one byte data via I2C data/clock
3279 for (i = 7; i >= 0; i--) { in e1000_clock_out_i2c_byte()
3298 * e1000_get_i2c_ack - Polls for I2C ACK
3301 * Clocks in/out one bit via I2C data/clock
3330 DEBUGOUT("I2C ack was not received.\n"); in e1000_get_i2c_ack()
3343 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3347 * Clocks in one bit via I2C data/clock
3370 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3374 * Clocks out one bit via I2C data/clock
3398 DEBUGOUT1("I2C data was not set to %X\n", data); in e1000_clock_out_i2c_bit()
3404 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3408 * Raises the I2C clock line '0'->'1'
3424 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3428 * Lowers the I2C clock line '1'->'0'
3445 * e1000_set_i2c_data - Sets the I2C data bit
3448 * @data: I2C data value (0 or 1) to set
3450 * Sets the I2C data bit
3468 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ in e1000_set_i2c_data()
3474 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); in e1000_set_i2c_data()
3481 * e1000_get_i2c_data - Reads the I2C SDA data bit
3484 * Returns the I2C data bit value
3501 * e1000_i2c_bus_clear - Clears the I2C bus
3504 * Clears the I2C bus by sending nine clock pulses.
3532 /* Put the i2c bus back to default state */ in e1000_i2c_bus_clear()