Lines Matching +full:25 +full:gbase +full:- +full:sr
1 /*-
2 * Copyright (c) 2015-2016 Chelsio Communications, Inc.
65 {0x4000, "Chelsio T440-dbg"},
66 {0x4001, "Chelsio T420-CR"},
67 {0x4002, "Chelsio T422-CR"},
68 {0x4003, "Chelsio T440-CR"},
69 {0x4004, "Chelsio T420-BCH"},
70 {0x4005, "Chelsio T440-BCH"},
71 {0x4006, "Chelsio T440-CH"},
72 {0x4007, "Chelsio T420-SO"},
73 {0x4008, "Chelsio T420-CX"},
74 {0x4009, "Chelsio T420-BT"},
75 {0x400a, "Chelsio T404-BT"},
76 {0x400e, "Chelsio T440-LP-CR"},
78 {0x5000, "Chelsio T580-dbg"},
79 {0x5001, "Chelsio T520-CR"}, /* 2 x 10G */
80 {0x5002, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
81 {0x5003, "Chelsio T540-CR"}, /* 4 x 10G */
82 {0x5007, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
83 {0x5009, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
84 {0x500a, "Chelsio T504-BT"}, /* 4 x 1G */
85 {0x500d, "Chelsio T580-CR"}, /* 2 x 40G */
86 {0x500e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
87 {0x5010, "Chelsio T580-LP-CR"}, /* 2 x 40G */
88 {0x5011, "Chelsio T520-LL-CR"}, /* 2 x 10G */
89 {0x5012, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
90 {0x5014, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
91 {0x5015, "Chelsio T502-BT"}, /* 2 x 1G */
92 {0x5018, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
93 {0x5019, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
94 {0x501a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
95 {0x501b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
97 {0x6000, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
98 {0x6001, "Chelsio T6225-CR"}, /* 2 x 10/25G */
99 {0x6002, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
100 {0x6003, "Chelsio T6425-CR"}, /* 4 x 10/25G */
101 {0x6004, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
102 {0x6005, "Chelsio T6225-SO-OCP3"}, /* 2 x 10/25G, nomem */
103 {0x6006, "Chelsio T6225-OCP3"}, /* 2 x 10/25G */
104 {0x6007, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
105 {0x6008, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
106 {0x6009, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
107 {0x600d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
108 {0x6010, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
109 {0x6011, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
110 {0x6014, "Chelsio T62100-SO-OCP3"}, /* 2 x 40/50/100G, nomem */
111 {0x6015, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
116 {0x6082, "Chelsio T6225-CR 82"},
117 {0x6083, "Chelsio T62100-CR 83"},
118 {0x6084, "Chelsio T64100-CR 84"},
119 {0x6085, "Chelsio T6240-SO 85"},
120 {0x6086, "Chelsio T6225-SO-CR 86"},
121 {0x6087, "Chelsio T6225-CR 87"},
124 {0x7000, "Chelsio T72200-DBG"}, /* 2 x 200G, debug */
125 {0x7001, "Chelsio T7250"}, /* 2 x 10/25/50G, 1 mem */
126 {0x7002, "Chelsio S7250"}, /* 2 x 10/25/50G, nomem */
127 {0x7003, "Chelsio T7450"}, /* 4 x 10/25/50G, 1 mem */
128 {0x7004, "Chelsio S7450"}, /* 4 x 10/25/50G, nomem */
131 {0x7007, "Chelsio T72200-FH"}, /* 2 x 40/100/200G, 2 mem */
133 {0x7009, "Chelsio S7210-BT"}, /* 2 x 10GBASE-T, nomem */
134 {0x700a, "Chelsio T7450-RC"}, /* 4 x 10/25/50G, 1 mem, RC */
135 {0x700b, "Chelsio T72200-RC"}, /* 2 x 40/100/200G, 1 mem, RC */
136 {0x700c, "Chelsio T72200-FH-RC"}, /* 2 x 40/100/200G, 2 mem, RC */
137 {0x700d, "Chelsio S72200-OCP3"}, /* 2 x 40/100/200G OCP3 */
138 {0x700e, "Chelsio S7450-OCP3"}, /* 4 x 1/20/25/50G OCP3 */
139 {0x700f, "Chelsio S7410-BT-OCP3"}, /* 4 x 10GBASE-T OCP3 */
140 {0x7010, "Chelsio S7210-BT-A"}, /* 2 x 10GBASE-T */
150 return bus_space_read_4(sc->bt, sc->bh, reg);
243 sc->sc_dev = dev;
245 sc->regs_rid = PCIR_BAR(0);
246 sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
247 &sc->regs_rid, RF_ACTIVE);
248 if (sc->regs_res == NULL) {
252 sc->bt = rman_get_bustag(sc->regs_res);
253 sc->bh = rman_get_bushandle(sc->regs_res);
258 sc->pf = G_SOURCEPF(whoami);
260 sc->pf = G_T6_SOURCEPF(whoami);
262 sc->sc_main = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
264 if (sc->sc_main == NULL) {
265 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
266 sc->regs_res);
269 if (T4_IS_MAIN_READY(sc->sc_main) == 0) {
272 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
273 sc->regs_res);
290 MPASS(!sc->sc_attached);
293 * PF0-3 are associated with a specific port on the NIC (PF0
298 error = T4_READ_PORT_DEVICE(sc->sc_main, pci_get_function(dev), &pdev);
305 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL);
310 device_printf(dev, "Failed to initialize SR-IOV: %d\n", error);
315 sc->sc_attached = true;
328 if (!sc->sc_attached)
334 device_printf(dev, "Failed to disable SR-IOV\n");
339 sc->sc_attached = false;
350 if (sc->sc_attached) {
355 if (sc->regs_res) {
356 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
357 sc->regs_res);
387 MPASS(sc->sc_attached);
388 MPASS(sc->sc_main != NULL);
389 adap = device_get_softc(sc->sc_main);
391 if (nvlist_exists_binary(config, "mac-addr")) {
392 mac = nvlist_get_binary(config, "mac-addr", &size);
398 rc = -t4_set_vf_mac(adap, sc->pf, vfnum + 1, 1, ma);
422 rc = t4_set_vlan_acl(adap, sc->pf, vfnum + 1, vlan);