Lines Matching +full:0 +full:x00000400
23 reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if
28 reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch
31 # queues, and 0xfff for LP which
36 reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which
42 reg[0x7d04] = 0x00010000/0x00010000
45 reg[0x7d6c] = 0x00000000/0x00007000
48 reg[0x7d78] = 0x00000400/0x00000000
50 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
58 # TP number of RX channels (0 = auto)
59 tp_nrxch = 0
64 # TP number of TX channels (0 = auto)
65 tp_ntxch = 0
71 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
74 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
77 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
83 mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
84 mc_mode_brc[1] = 1 # mc1 - 1: enable BRC, 0: enable RBC
87 reg[0x8dc0] = 0x00000004/0x00000004 # Enable more error msg for ...
90 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
92 [function "0"]
96 rssnvi = 0
102 pmask = 0x1
108 rssnvi = 0
114 pmask = 0x2
120 rssnvi = 0
126 pmask = 0x4
132 rssnvi = 0
138 pmask = 0x8
179 rssnvi = 0
185 rssnvi = 0
194 rssnvi = 0
206 [function "0/*"]
207 wx_caps = 0x82
208 r_caps = 0x86
210 rssnvi = 0
216 pmask = 0x1
219 wx_caps = 0x82
220 r_caps = 0x86
222 rssnvi = 0
228 pmask = 0x2
231 wx_caps = 0x82
232 r_caps = 0x86
234 rssnvi = 0
240 pmask = 0x4
243 wx_caps = 0x82
244 r_caps = 0x86
246 rssnvi = 0
252 pmask = 0x8
256 [port "0"]
289 version = 0x1
290 checksum = 0x34da8705