Lines Matching +full:lo +full:- +full:buff +full:- +full:en
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
48 * t4_wait_op_done_val - wait until an operation is completed
51 * @mask: a single-bit field within @reg that indicates completion
60 * operation completes and -EAGAIN otherwise.
73 if (--attempts == 0) in t4_wait_op_done_val()
74 return -EAGAIN; in t4_wait_op_done_val()
88 * t7_wait_sram_done - wait until an operation is completed
99 * operation completes successfully and -EAGAIN if it times out.
114 if (--attempts == 0) in t7_wait_sram_done()
115 return -EAGAIN; in t7_wait_sram_done()
123 * t4_set_reg_field - set a register field to a value
142 * t4_read_indirect - read indirectly addressed registers
157 while (nregs--) { in t4_read_indirect()
165 * t4_write_indirect - write indirectly addressed registers
180 while (nregs--) { in t4_write_indirect()
187 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
198 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); in t4_hw_pci_read_cfg4()
216 * read-modify-write via t4_set_reg_field().) in t4_hw_pci_read_cfg4()
224 * t4_report_fw_error - report firmware error
253 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
258 for ( ; nflit; nflit--, mbox_addr += 8) in get_mbox_rpl()
269 asrt->u.assert.filename_0_7, in fw_asrt()
270 be32_to_cpu(asrt->u.assert.line), in fw_asrt()
271 be32_to_cpu(asrt->u.assert.x), in fw_asrt()
272 be32_to_cpu(asrt->u.assert.y)); in fw_asrt()
298 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg); in read_tx_state_one()
299 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg); in read_tx_state_one()
308 if (sc->chan_map[i] != 0xff) in read_tx_state()
321 if (sc->chan_map[i] == 0xff) in check_tx_state()
340 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
387 if (adap->flags & CHK_MBOX_ACCESS) in t4_wr_mbox_meat_timeout()
391 return -EINVAL; in t4_wr_mbox_meat_timeout()
393 if (adap->flags & IS_VF) { in t4_wr_mbox_meat_timeout()
406 timeout = -timeout; in t4_wr_mbox_meat_timeout()
413 if (!(adap->flags & IS_VF)) { in t4_wr_mbox_meat_timeout()
429 if (!(adap->flags & IS_VF)) { in t4_wr_mbox_meat_timeout()
434 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; in t4_wr_mbox_meat_timeout()
458 if (adap->flags & IS_VF) { in t4_wr_mbox_meat_timeout()
464 * to the VF's PL-register-backed Mailbox Control can in t4_wr_mbox_meat_timeout()
465 * race in front of the writes to the MA-backed VF in t4_wr_mbox_meat_timeout()
467 * read-back on at least one byte of the VF Mailbox in t4_wr_mbox_meat_timeout()
485 if (!(adap->flags & IS_VF)) { in t4_wr_mbox_meat_timeout()
498 if (delay_idx < ARRAY_SIZE(delay) - 1) in t4_wr_mbox_meat_timeout()
528 return -G_FW_CMD_RETVAL((int)res); in t4_wr_mbox_meat_timeout()
542 adap->flags &= ~FW_OK; in t4_wr_mbox_meat_timeout()
543 ret = pcie_fw & F_PCIE_FW_ERR ? -ENXIO : -ETIMEDOUT; in t4_wr_mbox_meat_timeout()
593 * t4_mc_read - read from MC through backdoor accesses
598 * @ecc: where to store the corresponding 64-bit ECC word
600 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
602 * is assigned the 64-bit ECC word for the read data.
624 return (-ENOTSUP); in t4_mc_read()
628 return -EBUSY; in t4_mc_read()
640 for (i = 15; i >= 0; i--) in t4_mc_read()
649 * t4_edc_read - read from EDC through backdoor accesses
654 * @ecc: where to store the corresponding 64-bit ECC word
656 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
658 * is assigned the 64-bit ECC word for the read data.
685 return -EBUSY; in t4_edc_read()
697 for (i = 15; i >= 0; i--) in t4_edc_read()
706 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer
715 * 32-bit boudaries. The memory is returned as a raw byte sequence from
717 * contain multi-byte integers, it's the callers responsibility to
730 return -EINVAL; in t4_mem_read()
735 * copying out of the first line at (addr - start) a word at a time. in t4_mem_read()
739 offset = (addr - start)/sizeof(__be32); in t4_mem_read()
748 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); in t4_mem_read()
759 len -= sizeof(__be32); in t4_mem_read()
767 * Return the specified PCI-E Configuration Space register from our Physical
777 * retrieve the specified PCI-E Configuration Space register. in t4_read_pcie_cfg4()
792 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); in t4_read_pcie_cfg4()
799 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), in t4_read_pcie_cfg4()
806 reg, -ret); in t4_read_pcie_cfg4()
810 * Read the desired Configuration Space register via the PCI-E in t4_read_pcie_cfg4()
817 * t4_get_regs_len - return the size of the chips register set
828 if (adapter->flags & IS_VF) in t4_get_regs_len()
835 if (adapter->flags & IS_VF) in t4_get_regs_len()
846 * t4_get_regs - read chip registers into provided buffer
1325 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), in t4_get_regs()
2102 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), in t4_get_regs()
2672 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), in t4_get_regs()
3324 if (adap->flags & IS_VF) { in t4_get_regs()
3334 if (adap->flags & IS_VF) { in t4_get_regs()
3344 if (adap->flags & IS_VF) { in t4_get_regs()
3354 if (adap->flags & IS_VF) { in t4_get_regs()
3392 * header followed by one or more VPD-R sections, each with its own header.
3421 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
3424 * Request before any in-flight VPD reguest has completed.
3428 unsigned int base = adapter->params.pci.vpd_cap_addr; in t4_seeprom_wait()
3435 if (!adapter->vpd_busy) in t4_seeprom_wait()
3453 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { in t4_seeprom_wait()
3454 adapter->vpd_busy = 0; in t4_seeprom_wait()
3457 } while (--max_poll); in t4_seeprom_wait()
3466 return -ETIMEDOUT; in t4_seeprom_wait()
3470 * t4_seeprom_read - read a serial EEPROM location
3475 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
3481 unsigned int base = adapter->params.pci.vpd_cap_addr; in t4_seeprom_read()
3485 * VPD Accesses must alway be 4-byte aligned! in t4_seeprom_read()
3488 return -EINVAL; in t4_seeprom_read()
3507 adapter->vpd_busy = 1; in t4_seeprom_read()
3508 adapter->vpd_flag = PCI_VPD_ADDR_F; in t4_seeprom_read()
3525 * t4_seeprom_write - write a serial EEPROM location
3530 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
3536 unsigned int base = adapter->params.pci.vpd_cap_addr; in t4_seeprom_write()
3542 * VPD Accesses must alway be 4-byte aligned! in t4_seeprom_write()
3545 return -EINVAL; in t4_seeprom_write()
3567 adapter->vpd_busy = 1; in t4_seeprom_write()
3568 adapter->vpd_flag = 0; in t4_seeprom_write()
3584 } while ((stats_reg & 0x1) && --max_poll); in t4_seeprom_write()
3586 return -ETIMEDOUT; in t4_seeprom_write()
3593 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
3596 * @sz: size of function-specific area
3603 * [0..1K) -> [31K..32K)
3604 * [1K..1K+A) -> [ES-A..ES)
3605 * [1K+A..ES) -> [0..ES-A-1K)
3615 return EEPROMSIZE - fn + phys_addr - 1024; in t4_eeprom_ptov()
3617 return phys_addr - 1024 - fn; in t4_eeprom_ptov()
3618 return -EINVAL; in t4_eeprom_ptov()
3622 * t4_seeprom_wp - enable/disable EEPROM write protection
3634 * get_vpd_keyword_val - Locates an information field keyword in the VPD
3640 * -ENOENT otherwise.
3650 tag = vpdr->vpdr_tag; in get_vpd_keyword_val()
3651 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); in get_vpd_keyword_val()
3652 while (region--) { in get_vpd_keyword_val()
3655 if (++tag != vpdr->vpdr_tag) in get_vpd_keyword_val()
3656 return -ENOENT; in get_vpd_keyword_val()
3657 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); in get_vpd_keyword_val()
3662 return -ENOENT; in get_vpd_keyword_val()
3674 return -ENOENT; in get_vpd_keyword_val()
3679 * get_vpd_params - read VPD parameters from VPD EEPROM
3721 return -EINVAL; \ in get_vpd_params()
3726 for (csum = 0; i >= 0; i--) in get_vpd_params()
3732 return -EINVAL; in get_vpd_params()
3741 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); in get_vpd_params()
3742 strstrip(p->id); in get_vpd_params()
3743 memcpy(p->ec, vpd + ec, EC_LEN); in get_vpd_params()
3744 strstrip(p->ec); in get_vpd_params()
3745 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; in get_vpd_params()
3746 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); in get_vpd_params()
3747 strstrip(p->sn); in get_vpd_params()
3748 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; in get_vpd_params()
3749 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); in get_vpd_params()
3750 strstrip((char *)p->pn); in get_vpd_params()
3751 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; in get_vpd_params()
3752 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); in get_vpd_params()
3753 strstrip((char *)p->na); in get_vpd_params()
3760 snprintf(p->md, sizeof(p->md), "unknown"); in get_vpd_params()
3762 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; in get_vpd_params()
3763 memcpy(p->md, vpd + md, min(i, MD_LEN)); in get_vpd_params()
3764 strstrip((char *)p->md); in get_vpd_params()
3816 *lenp = FLASH_MAX_SIZE(l->nsecs); in t4_flash_loc_start()
3817 return (FLASH_START(l->start_sec)); in t4_flash_loc_start()
3835 * sf1_read - read data from the serial flash
3853 return -EINVAL; in sf1_read()
3855 return -EBUSY; in sf1_read()
3856 op = V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1); in sf1_read()
3867 * sf1_write - write data to the serial flash
3882 return -EINVAL; in sf1_write()
3884 return -EBUSY; in sf1_write()
3887 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); in sf1_write()
3892 * flash_wait_op - wait for a flash operation to complete
3910 if (--attempts == 0) in flash_wait_op()
3911 return -EAGAIN; in flash_wait_op()
3918 * t4_read_flash - read words from serial flash
3921 * @nwords: how many 32-bit words to read
3925 * Read the specified number of 32-bit words from the serial flash.
3927 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3935 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) in t4_read_flash()
3936 return -EINVAL; in t4_read_flash()
3944 for ( ; nwords; nwords--, data++) { in t4_read_flash()
3957 * t4_write_flash - write up to a page of data to the serial flash
3967 * (i.e. matches what on disk), otherwise in big-endian.
3976 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) in t4_write_flash()
3977 return -EINVAL; in t4_write_flash()
3985 for (left = n; left; left -= c) { in t4_write_flash()
4009 if (memcmp(data - n, (u8 *)buf + offset, n)) { in t4_write_flash()
4013 return -EIO; in t4_write_flash()
4023 * t4_get_fw_version - read the firmware version
4038 * t4_get_fw_hdr - read the firmware header
4053 * t4_get_bs_version - read the firmware bootstrap version
4069 * t4_get_tp_version - read the TP microcode version
4084 * t4_get_exprom_version - return the Expansion ROM version (if any)
4091 * 0 on success, -ENOENT if no Expansion ROM is present.
4110 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) in t4_get_exprom_version()
4111 return -ENOENT; in t4_get_exprom_version()
4113 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | in t4_get_exprom_version()
4114 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | in t4_get_exprom_version()
4115 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | in t4_get_exprom_version()
4116 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); in t4_get_exprom_version()
4121 * t4_get_scfg_version - return the Serial Configuration version
4131 * to retrieve the Serial Configuration version, so we zero-out the
4132 * return-value parameter in that case to avoid leaving it with
4150 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, in t4_get_scfg_version()
4158 * t4_get_vpd_version - return the VPD version
4168 * to retrieve the VPD version, so we zero-out the return-value parameter
4185 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, in t4_get_vpd_version()
4193 * t4_get_version_info - extract various chip/firmware version information
4212 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); in t4_get_version_info()
4213 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); in t4_get_version_info()
4214 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); in t4_get_version_info()
4215 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); in t4_get_version_info()
4216 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); in t4_get_version_info()
4217 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); in t4_get_version_info()
4225 * t4_flash_erase_sectors - erase a range of flash sectors
4236 if (end >= adapter->params.sf_nsec) in t4_flash_erase_sectors()
4237 return -EINVAL; in t4_flash_erase_sectors()
4256 * t4_flash_cfg_addr - return the address of the flash configuration file
4272 if (adapter->params.sf_size < cfg_start + len) in t4_flash_cfg_addr()
4273 return -ENOSPC; in t4_flash_cfg_addr()
4292 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || in t4_fw_matches_chip()
4293 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || in t4_fw_matches_chip()
4294 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6) || in t4_fw_matches_chip()
4295 (is_t7(adap) && hdr->chip == FW_HDR_CHIP_T7)) in t4_fw_matches_chip()
4300 hdr->chip, chip_id(adap)); in t4_fw_matches_chip()
4305 * t4_load_fw - download firmware
4325 loc = ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP ? in t4_load_fw()
4332 return -EINVAL; in t4_load_fw()
4337 return -EINVAL; in t4_load_fw()
4339 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { in t4_load_fw()
4342 return -EINVAL; in t4_load_fw()
4347 return -EFBIG; in t4_load_fw()
4350 return -EINVAL; in t4_load_fw()
4358 return -EINVAL; in t4_load_fw()
4362 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); in t4_load_fw()
4372 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); in t4_load_fw()
4378 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { in t4_load_fw()
4388 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); in t4_load_fw()
4397 * t4_fwcache - firmware cache operation
4409 V_FW_PARAMS_CMD_PFN(adap->pf) | in t4_fwcache()
4417 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); in t4_fwcache()
4491 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
4492 * @caps16: a 16-bit Port Capabilities value
4494 * Returns the equivalent 32-bit Port Capabilities value.
4529 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4530 * @caps32: a 32-bit Port Capabilities value
4532 * Returns the equivalent 16-bit Port Capabilities value. Note that
4533 * not all 32-bit Port Capabilities can be represented in the 16-bit
4606 * t4_link_l1cfg - apply link configuration to MAC/PHY
4612 * - If the PHY can auto-negotiate first decide what to advertise, then
4613 * enable/disable auto-negotiation as desired, and reset.
4614 * - If the PHY does not auto-negotiate just reset it.
4615 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4616 * otherwise do it later based on the outcome of auto-negotiation.
4626 if (lc->requested_fc & PAUSE_RX) in t4_link_l1cfg()
4628 if (lc->requested_fc & PAUSE_TX) in t4_link_l1cfg()
4630 if (!(lc->requested_fc & PAUSE_AUTONEG)) in t4_link_l1cfg()
4633 if (lc->requested_aneg == AUTONEG_DISABLE) in t4_link_l1cfg()
4635 else if (lc->requested_aneg == AUTONEG_ENABLE) in t4_link_l1cfg()
4638 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; in t4_link_l1cfg()
4641 speed = lc->pcaps & in t4_link_l1cfg()
4643 } else if (lc->requested_speed != 0) in t4_link_l1cfg()
4644 speed = speed_to_fwcap(lc->requested_speed); in t4_link_l1cfg()
4646 speed = fwcap_top_speed(lc->pcaps); in t4_link_l1cfg()
4652 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) in t4_link_l1cfg()
4653 force_fec = lc->force_fec; in t4_link_l1cfg()
4657 if (lc->requested_fec == FEC_AUTO) { in t4_link_l1cfg()
4680 fec |= fec_to_fwcap(lc->fec_hint); in t4_link_l1cfg()
4700 fec |= fec_to_fwcap(lc->requested_fec & in t4_link_l1cfg()
4702 if (lc->requested_fec & FEC_MODULE) in t4_link_l1cfg()
4703 fec |= fec_to_fwcap(lc->fec_hint); in t4_link_l1cfg()
4716 if (isset(&adap->bt_map, port)) in t4_link_l1cfg()
4717 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; in t4_link_l1cfg()
4720 if ((rcap | lc->pcaps) != lc->pcaps) { in t4_link_l1cfg()
4723 lc->pcaps, rcap & (rcap ^ lc->pcaps)); in t4_link_l1cfg()
4725 rcap &= lc->pcaps; in t4_link_l1cfg()
4733 if (adap->params.port_caps32) { in t4_link_l1cfg()
4745 lc->requested_caps = rcap; in t4_link_l1cfg()
4750 * t4_restart_aneg - restart autonegotiation
4801 return ('-'); in intr_alert_char()
4816 ii->name, ii->cause_reg, cause, enabled, fatal); in show_intr_info()
4820 for (details = ii->details; details && details->mask != 0; details++) { in show_intr_info()
4821 msgbits = details->mask & leftover; in show_intr_info()
4825 CH_ALERT(sc, " %c [0x%08x] %s\n", alert, msgbits, details->msg); in show_intr_info()
4843 cause = t4_read_reg(sc, ii->cause_reg); in t4_handle_intr()
4844 enabled = t4_read_reg(sc, ii->enable_reg); in t4_handle_intr()
4845 flags |= ii->flags; in t4_handle_intr()
4846 fatal = ii->fatal & cause; in t4_handle_intr()
4856 for (action = ii->actions; action && action->mask != 0; action++) { in t4_handle_intr()
4857 if (action->action == NULL) in t4_handle_intr()
4859 if (action->mask & (ucause | acause) || in t4_handle_intr()
4861 bool rc1 = (action->action)(sc, action->arg, flags); in t4_handle_intr()
4862 if (action->mask & ucause) in t4_handle_intr()
4870 t4_write_reg(sc, ii->cause_reg, cause); in t4_handle_intr()
4871 (void)t4_read_reg(sc, ii->cause_reg); in t4_handle_intr()
4873 t4_write_reg(sc, ii->cause_reg, ucause); in t4_handle_intr()
4874 (void)t4_read_reg(sc, ii->cause_reg); in t4_handle_intr()
4929 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" }, in pcie_intr_handler()
4930 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" }, in pcie_intr_handler()
4931 { F_MSIXDATAPERR, "MSI-X data parity error" }, in pcie_intr_handler()
4932 { F_MSIXDIPERR, "MSI-X DI parity error" }, in pcie_intr_handler()
4960 { F_NONFATALERR, "PCIe non-fatal error" }, in pcie_intr_handler()
4983 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" }, in pcie_intr_handler()
4984 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" }, in pcie_intr_handler()
4985 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" }, in pcie_intr_handler()
4986 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" }, in pcie_intr_handler()
4987 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" }, in pcie_intr_handler()
5160 "SGE GTS with timer 0-5 for IQID > 1023" }, in sge_intr_handler()
5165 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, in sge_intr_handler()
5195 "SGE GTS with timer 0-5 for IQID > 1023" }, in sge_intr_handler()
5200 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, in sge_intr_handler()
5322 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" }, in cim_intr_handler()
5340 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" }, in cim_intr_handler()
5346 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" }, in cim_intr_handler()
5657 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i, in pmtx_dump_dbg_stats()
5673 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" }, in pmtx_intr_handler()
5687 { 0xffffffff, -1, pmtx_dump_dbg_stats }, in pmtx_intr_handler()
5717 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" }, in pmrx_intr_handler()
5759 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" }, in cplsw_intr_handler()
5809 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" }, in le_intr_handler()
5810 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" }, in le_intr_handler()
5811 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" }, in le_intr_handler()
5812 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" }, in le_intr_handler()
5915 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" }, in mps_intr_handler()
6216 " MA address wrap-around by client %u to address %#x\n", in ma_wrap_status()
6296 * NC-SI interrupt handler.
6301 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" }, in ncsi_intr_handler()
6302 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" }, in ncsi_intr_handler()
6303 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" }, in ncsi_intr_handler()
6304 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" }, in ncsi_intr_handler()
6508 { F_TIMEOUT, -1, pl_timeout_status }, in plpl_intr_handler()
6530 return (instance * (CRYPTO_1_BASE_ADDR - CRYPTO_0_BASE_ADDR) + in t7_tlstx_reg()
6620 { F_SEQ_WRAP_HP_OVFL, "Sequence wrap (hi-pri)" }, in cryptokey_intr_handler()
6621 { F_SEQ_WRAP_LP_OVFL, "Sequence wrap (lo-pri)" }, in cryptokey_intr_handler()
6622 { F_EGR_SEQ_WRAP_HP, "Egress sequence wrap (hi-pri)" }, in cryptokey_intr_handler()
6623 { F_EGR_SEQ_WRAP_LP, "Egress sequence wrap (lo-pri)" }, in cryptokey_intr_handler()
6787 cause = t4_read_reg(sc, ii->cause_reg); in get_perr_ucause()
6788 if (ii->flags & IHF_IGNORE_IF_DISABLED) in get_perr_ucause()
6789 cause &= t4_read_reg(sc, ii->enable_reg); in get_perr_ucause()
6798 if (adap->chip_params->nchan > 2) in t4_perr_to_ic()
6888 * t4_slow_intr_handler - control path interrupt handler
6891 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
6922 { F_NCSI, "NC-SI" }, in t4_slow_intr_handler()
6931 { F_ULP_TX, -1, ulptx_intr_handler }, in t4_slow_intr_handler()
6932 { F_SGE, -1, sge_intr_handler }, in t4_slow_intr_handler()
6933 { F_CPL_SWITCH, -1, cplsw_intr_handler }, in t4_slow_intr_handler()
6934 { F_ULP_RX, -1, ulprx_intr_handler }, in t4_slow_intr_handler()
6935 { F_PM_RX, -1, pmtx_intr_handler }, in t4_slow_intr_handler()
6936 { F_PM_TX, -1, pmtx_intr_handler }, in t4_slow_intr_handler()
6937 { F_MA, -1, ma_intr_handler }, in t4_slow_intr_handler()
6938 { F_TP, -1, tp_intr_handler }, in t4_slow_intr_handler()
6939 { F_LE, -1, le_intr_handler }, in t4_slow_intr_handler()
6944 { F_PCIE, -1, pcie_intr_handler }, in t4_slow_intr_handler()
6949 { F_SMB, -1, smb_intr_handler }, in t4_slow_intr_handler()
6950 { F_PL, -1, plpl_intr_handler }, in t4_slow_intr_handler()
6951 { F_NCSI, -1, ncsi_intr_handler }, in t4_slow_intr_handler()
6952 { F_MPS, -1, mps_intr_handler }, in t4_slow_intr_handler()
6953 { F_CIM, -1, cim_intr_handler }, in t4_slow_intr_handler()
7001 { F_NCSI, "NC-SI" }, in t4_slow_intr_handler()
7010 { F_T7_ULP_TX, -1, ulptx_intr_handler }, in t4_slow_intr_handler()
7011 { F_T7_SGE, -1, sge_intr_handler }, in t4_slow_intr_handler()
7012 { F_T7_HMA, -1, hma_intr_handler }, in t4_slow_intr_handler()
7013 { F_T7_CPL_SWITCH, -1, cplsw_intr_handler }, in t4_slow_intr_handler()
7014 { F_T7_ULP_RX, -1, ulprx_intr_handler }, in t4_slow_intr_handler()
7015 { F_T7_PM_RX, -1, pmrx_intr_handler }, in t4_slow_intr_handler()
7016 { F_T7_PM_TX, -1, pmtx_intr_handler }, in t4_slow_intr_handler()
7017 { F_T7_MA, -1, ma_intr_handler }, in t4_slow_intr_handler()
7018 { F_T7_TP, -1, tp_intr_handler }, in t4_slow_intr_handler()
7019 { F_T7_LE, -1, le_intr_handler }, in t4_slow_intr_handler()
7024 { F_T7_PCIE, -1, pcie_intr_handler }, in t4_slow_intr_handler()
7029 { F_SMB, -1, smb_intr_handler }, in t4_slow_intr_handler()
7030 { F_PL, -1, plpl_intr_handler }, in t4_slow_intr_handler()
7031 { F_NCSI, -1, ncsi_intr_handler }, in t4_slow_intr_handler()
7032 { F_MPS, -1, mps_intr_handler }, in t4_slow_intr_handler()
7033 { F_CIM, -1, cim_intr_handler }, in t4_slow_intr_handler()
7054 { F_CRYPTO_KEY, -1, cryptokey_intr_handler }, in t4_slow_intr_handler()
7057 { F_GCACHE, -1, gcache_intr_handler }, in t4_slow_intr_handler()
7058 { F_ARM, -1, arm_intr_handler }, in t4_slow_intr_handler()
7097 { F_T7_PL_PERR_NCSI, "NC-SI" }, in t4_slow_intr_handler()
7150 * t4_intr_enable - enable interrupts
7153 * Enable PF-specific interrupts for the calling function and the top-level
7159 * non PF-specific interrupts from the various HW modules. Only one PCI
7166 if (adap->intr_flags & IHF_INTR_CLEAR_ON_INIT) in t4_intr_enable()
7188 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf); in t4_intr_enable()
7192 * t4_intr_disable - disable interrupts
7195 * Disable interrupts. We only disable the top-level interrupt
7203 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0); in t4_intr_disable()
7207 * hash_mac_addr - return the hash value of a MAC address
7208 * @addr: the 48-bit Ethernet MAC address
7224 * t4_config_rss_range - configure a portion of the RSS mapping table
7257 * a 32-bit word as 10-bit values with the upper remaining 2 bits in t4_config_rss_range()
7276 n -= nq; in t4_config_rss_range()
7288 * current 3-tuple position within the commad. in t4_config_rss_range()
7294 nq -= nqbuf; in t4_config_rss_range()
7297 nqbuf--; in t4_config_rss_range()
7320 * t4_config_glbl_rss - configure the global RSS mode
7324 * @flags: mode-specific flags
7345 return -EINVAL; in t4_config_glbl_rss()
7350 * t4_config_vi_rss - configure per VI RSS settings
7356 * @skeyidx: RSS secret key table index for non-global mode
7359 * Configures VI-specific RSS properties.
7396 * t4_read_rss - read the contents of the RSS mapping table
7400 * Reads the contents of the RSS hash->queue mapping table.
7406 int rss_nentries = adapter->chip_params->rss_nentries; in t4_read_rss()
7419 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
7449 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, in t4_tp_fw_ldst_rw()
7461 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
7465 * @buff: where the indirect register values are stored/written
7475 u32 *buff, u32 nregs, u32 start_index, int rw, in t4_tp_indirect_rw() argument
7478 int rc = -EINVAL; in t4_tp_indirect_rw()
7496 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, in t4_tp_indirect_rw()
7503 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, in t4_tp_indirect_rw()
7506 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, in t4_tp_indirect_rw()
7512 * t4_tp_pio_read - Read TP PIO registers
7514 * @buff: where the indirect register values are written
7521 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, in t4_tp_pio_read() argument
7524 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, in t4_tp_pio_read()
7529 * t4_tp_pio_write - Write TP PIO registers
7531 * @buff: where the indirect register values are stored
7538 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, in t4_tp_pio_write() argument
7542 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); in t4_tp_pio_write()
7546 * t4_tp_tm_pio_read - Read TP TM PIO registers
7548 * @buff: where the indirect register values are written
7555 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, in t4_tp_tm_pio_read() argument
7558 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, in t4_tp_tm_pio_read()
7563 * t4_tp_mib_read - Read TP MIB registers
7565 * @buff: where the indirect register values are written
7572 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, in t4_tp_mib_read() argument
7575 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, in t4_tp_mib_read()
7580 * t4_read_rss_key - read the global RSS key
7582 * @key: 10-entry array holding the 320-bit RSS key
7585 * Reads the global 320-bit RSS key.
7593 * t4_write_rss_key - program one of the RSS keys
7595 * @key: 10-entry array holding the 320-bit RSS key
7599 * Writes one of the RSS keys with the given 320-bit value. If @idx is
7610 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), in t4_write_rss_key()
7611 * allows access to key addresses 16-63 by using KeyWrAddrX in t4_write_rss_key()
7632 * t4_read_rss_pf_config - read PF RSS Configuration Table
7648 * t4_write_rss_pf_config - write PF RSS Configuration Table
7665 * t4_read_rss_vf_config - read VF RSS Configuration Table
7703 * t4_write_rss_vf_config - write VF RSS Configuration Table
7742 * t4_read_rss_pf_map - read PF RSS Map
7758 * t4_write_rss_pf_map - write PF RSS Map
7770 * t4_read_rss_pf_mask - read PF RSS Mask
7786 * t4_write_rss_pf_mask - write PF RSS Mask
7798 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
7810 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; in t4_tp_get_tcp_stats()
7812 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) in t4_tp_get_tcp_stats()
7819 v4->tcp_out_rsts = STAT(OUT_RST); in t4_tp_get_tcp_stats()
7820 v4->tcp_in_segs = STAT64(IN_SEG); in t4_tp_get_tcp_stats()
7821 v4->tcp_out_segs = STAT64(OUT_SEG); in t4_tp_get_tcp_stats()
7822 v4->tcp_retrans_segs = STAT64(RXT_SEG); in t4_tp_get_tcp_stats()
7827 v6->tcp_out_rsts = STAT(OUT_RST); in t4_tp_get_tcp_stats()
7828 v6->tcp_in_segs = STAT64(IN_SEG); in t4_tp_get_tcp_stats()
7829 v6->tcp_out_segs = STAT64(OUT_SEG); in t4_tp_get_tcp_stats()
7830 v6->tcp_retrans_segs = STAT64(RXT_SEG); in t4_tp_get_tcp_stats()
7838 * t4_tp_get_err_stats - read TP's error MIB counters
7848 int nchan = adap->chip_params->nchan; in t4_tp_get_err_stats()
7850 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, in t4_tp_get_err_stats()
7853 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, in t4_tp_get_err_stats()
7856 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, in t4_tp_get_err_stats()
7859 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, in t4_tp_get_err_stats()
7862 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, in t4_tp_get_err_stats()
7865 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, in t4_tp_get_err_stats()
7868 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, in t4_tp_get_err_stats()
7871 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, in t4_tp_get_err_stats()
7874 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, in t4_tp_get_err_stats()
7879 * t4_tp_get_err_stats - read TP's error MIB counters
7889 int nchan = adap->chip_params->nchan; in t4_tp_get_tnl_stats()
7891 t4_tp_mib_read(adap, st->out_pkt, nchan, A_TP_MIB_TNL_OUT_PKT_0, in t4_tp_get_tnl_stats()
7893 t4_tp_mib_read(adap, st->in_pkt, nchan, A_TP_MIB_TNL_IN_PKT_0, in t4_tp_get_tnl_stats()
7898 * t4_tp_get_proxy_stats - read TP's proxy MIB counters
7907 int nchan = adap->chip_params->nchan; in t4_tp_get_proxy_stats()
7909 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); in t4_tp_get_proxy_stats()
7913 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
7923 int nchan = adap->chip_params->nchan; in t4_tp_get_cpl_stats()
7925 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); in t4_tp_get_cpl_stats()
7927 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); in t4_tp_get_cpl_stats()
7931 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
7940 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, in t4_tp_get_rdma_stats()
7945 t4_tp_mib_read(adap, &st->pkts_in[0], 28, A_TP_MIB_RDMA_IN_PKT_0, in t4_tp_get_rdma_stats()
7950 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
7963 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, in t4_get_fcoe_stats()
7966 t4_tp_mib_read(adap, &st->frames_drop, 1, in t4_get_fcoe_stats()
7972 st->octets_ddp = ((u64)val[0] << 32) | val[1]; in t4_get_fcoe_stats()
7976 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
7981 * Returns the values of TP's counters for non-TCP directly-placed packets.
7990 st->frames = val[0]; in t4_get_usm_stats()
7991 st->drops = val[1]; in t4_get_usm_stats()
7992 st->octets = ((u64)val[2] << 32) | val[3]; in t4_get_usm_stats()
7996 * t4_tp_get_tid_stats - read TP's tid MIB counters.
8007 t4_tp_mib_read(adap, &st->del, 4, A_TP_MIB_TID_DEL, sleep_ok); in t4_tp_get_tid_stats()
8011 * t4_read_mtu_tbl - returns the values in the HW path MTU table
8014 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
8034 * t4_read_cong_tbl - reads the congestion control table
8055 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
8072 * init_cong_ctrl - initialize congestion control parameters
8119 * t4_load_mtus - write the MTU and congestion control HW tables
8125 * Write the HW MTU table with the supplied MTUs and the high-speed
8146 log2--; in t4_load_mtus()
8153 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], in t4_load_mtus()
8163 * t4_set_pace_tbl - set the pace table
8178 return -ERANGE; in t4_set_pace_tbl()
8184 return -ERANGE; in t4_set_pace_tbl()
8186 return -ERANGE; in t4_set_pace_tbl()
8194 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler
8204 unsigned int clk = adap->params.vpd.cclk * 1000; in t4_set_sched_bps()
8208 kbps *= 125; /* -> bytes */ in t4_set_sched_bps()
8214 delta = v >= kbps ? v - kbps : kbps - v; in t4_set_sched_bps()
8224 return -EINVAL; in t4_set_sched_bps()
8227 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); in t4_set_sched_bps()
8238 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
8247 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; in t4_set_sched_ipg()
8253 return -EINVAL; in t4_set_sched_ipg()
8267 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
8278 u64 v = (u64)bytes256 * adap->params.vpd.cclk; in chan_rate()
8284 * t4_get_chan_txrate - get the current per channel Tx rates
8299 if (adap->chip_params->nchan > 2) { in t4_get_chan_txrate()
8307 if (adap->chip_params->nchan > 2) { in t4_get_chan_txrate()
8314 * t4_set_trace_filter - configure one of the tracing filters
8330 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; in t4_set_trace_filter() local
8333 return -EINVAL; in t4_set_trace_filter()
8344 t4_set_reg_field(adap, match_ctl_a, en, enable ? en : 0); in t4_set_trace_filter()
8349 * TODO - After T4 data book is updated, specify the exact in t4_set_trace_filter()
8352 * See T4 data book - MPS section for a complete description in t4_set_trace_filter()
8363 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) in t4_set_trace_filter()
8364 return -EINVAL; in t4_set_trace_filter()
8371 if (tp->snap_len > 9600 || idx) in t4_set_trace_filter()
8372 return -EINVAL; in t4_set_trace_filter()
8375 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || in t4_set_trace_filter()
8376 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || in t4_set_trace_filter()
8377 tp->min_len > M_TFMINPKTSIZE) in t4_set_trace_filter()
8378 return -EINVAL; in t4_set_trace_filter()
8381 t4_set_reg_field(adap, match_ctl_a, en, 0); in t4_set_trace_filter()
8383 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; in t4_set_trace_filter()
8388 t4_write_reg(adap, data_reg, tp->data[i]); in t4_set_trace_filter()
8389 t4_write_reg(adap, mask_reg, ~tp->mask[i]); in t4_set_trace_filter()
8391 t4_write_reg(adap, match_ctl_b, V_TFCAPTUREMAX(tp->snap_len) | in t4_set_trace_filter()
8392 V_TFMINPKTSIZE(tp->min_len)); in t4_set_trace_filter()
8393 t4_write_reg(adap, match_ctl_a, V_TFOFFSET(tp->skip_ofst) | in t4_set_trace_filter()
8394 V_TFLENGTH(tp->skip_len) | en | (is_t4(adap) ? in t4_set_trace_filter()
8395 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : in t4_set_trace_filter()
8396 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); in t4_set_trace_filter()
8402 * t4_get_trace_filter - query one of the tracing filters
8406 * @enabled: non-zero if the filter is enabled
8427 tp->port = G_TFPORT(ctla); in t4_get_trace_filter()
8428 tp->invert = !!(ctla & F_TFINVERTMATCH); in t4_get_trace_filter()
8431 tp->port = G_T5_TFPORT(ctla); in t4_get_trace_filter()
8432 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); in t4_get_trace_filter()
8434 tp->snap_len = G_TFCAPTUREMAX(ctlb); in t4_get_trace_filter()
8435 tp->min_len = G_TFMINPKTSIZE(ctlb); in t4_get_trace_filter()
8436 tp->skip_ofst = G_TFOFFSET(ctla); in t4_get_trace_filter()
8437 tp->skip_len = G_TFLENGTH(ctla); in t4_get_trace_filter()
8439 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; in t4_get_trace_filter()
8444 tp->mask[i] = ~t4_read_reg(adap, mask_reg); in t4_get_trace_filter()
8445 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; in t4_get_trace_filter()
8450 * t4_set_trace_rss_control - configure the trace rss control register
8481 * t4_pmtx_get_stats - returns the HW stats from PMTX
8493 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { in t4_pmtx_get_stats()
8510 * t4_pmrx_get_stats - returns the HW stats from PMRX
8522 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { in t4_pmrx_get_stats()
8537 * t4_pmrx_cache_get_stats - returns the HW PMRX cache stats
8556 * t4_get_mps_bg_map - return the buffer groups associated with a port
8568 if (adap->params.mps_bg_map != UINT32_MAX) in t4_get_mps_bg_map()
8569 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); in t4_get_mps_bg_map()
8571 n = adap->params.nports; in t4_get_mps_bg_map()
8581 * TP RX e-channels associated with the port.
8585 const u32 n = adap->params.nports; in t4_get_rx_e_chan_map()
8586 const u32 all_chan = (1 << adap->chip_params->nchan) - 1; in t4_get_rx_e_chan_map()
8588 switch (adap->params.tp.lb_mode) { in t4_get_rx_e_chan_map()
8603 adap->params.tp.lb_mode); in t4_get_rx_e_chan_map()
8609 * TP RX c-channel associated with the port.
8613 if (adap->params.tp_ch_map != UINT32_MAX) in t4_get_rx_c_chan()
8614 return (adap->params.tp_ch_map >> (8 * idx)) & 0xff; in t4_get_rx_c_chan()
8619 * TP TX c-channel associated with the port.
8623 if (adap->params.tx_tp_ch_map != UINT32_MAX) in t4_get_tx_c_chan()
8624 return (adap->params.tx_tp_ch_map >> (8 * idx)) & 0xff; in t4_get_tx_c_chan()
8629 * t4_get_port_type_description - return Port Type string description
8666 * t4_get_port_stats_offset - collect port stats relative to a previous
8684 *s -= *o; in t4_get_port_stats_offset()
8688 * t4_get_port_stats - collect port statistics
8701 port_id = adap->port_map[idx]; in t4_get_port_stats()
8702 MPASS(port_id >= 0 && port_id <= adap->params.nports); in t4_get_port_stats()
8703 pi = adap->port[port_id]; in t4_get_port_stats()
8709 for (tx_chan = pi->tx_chan; in t4_get_port_stats()
8710 tx_chan < pi->tx_chan + adap->params.tp.lb_nchan; tx_chan++) { in t4_get_port_stats()
8711 p->tx_pause += GET_STAT(TX_PORT_PAUSE); in t4_get_port_stats()
8712 p->tx_octets += GET_STAT(TX_PORT_BYTES); in t4_get_port_stats()
8713 p->tx_frames += GET_STAT(TX_PORT_FRAMES); in t4_get_port_stats()
8714 p->tx_bcast_frames += GET_STAT(TX_PORT_BCAST); in t4_get_port_stats()
8715 p->tx_mcast_frames += GET_STAT(TX_PORT_MCAST); in t4_get_port_stats()
8716 p->tx_ucast_frames += GET_STAT(TX_PORT_UCAST); in t4_get_port_stats()
8717 p->tx_error_frames += GET_STAT(TX_PORT_ERROR); in t4_get_port_stats()
8718 p->tx_frames_64 += GET_STAT(TX_PORT_64B); in t4_get_port_stats()
8719 p->tx_frames_65_127 += GET_STAT(TX_PORT_65B_127B); in t4_get_port_stats()
8720 p->tx_frames_128_255 += GET_STAT(TX_PORT_128B_255B); in t4_get_port_stats()
8721 p->tx_frames_256_511 += GET_STAT(TX_PORT_256B_511B); in t4_get_port_stats()
8722 p->tx_frames_512_1023 += GET_STAT(TX_PORT_512B_1023B); in t4_get_port_stats()
8723 p->tx_frames_1024_1518 += GET_STAT(TX_PORT_1024B_1518B); in t4_get_port_stats()
8724 p->tx_frames_1519_max += GET_STAT(TX_PORT_1519B_MAX); in t4_get_port_stats()
8725 p->tx_drop += GET_STAT(TX_PORT_DROP); in t4_get_port_stats()
8726 p->tx_ppp0 += GET_STAT(TX_PORT_PPP0); in t4_get_port_stats()
8727 p->tx_ppp1 += GET_STAT(TX_PORT_PPP1); in t4_get_port_stats()
8728 p->tx_ppp2 += GET_STAT(TX_PORT_PPP2); in t4_get_port_stats()
8729 p->tx_ppp3 += GET_STAT(TX_PORT_PPP3); in t4_get_port_stats()
8730 p->tx_ppp4 += GET_STAT(TX_PORT_PPP4); in t4_get_port_stats()
8731 p->tx_ppp5 += GET_STAT(TX_PORT_PPP5); in t4_get_port_stats()
8732 p->tx_ppp6 += GET_STAT(TX_PORT_PPP6); in t4_get_port_stats()
8733 p->tx_ppp7 += GET_STAT(TX_PORT_PPP7); in t4_get_port_stats()
8735 p->rx_pause += GET_STAT(RX_PORT_PAUSE); in t4_get_port_stats()
8736 p->rx_octets += GET_STAT(RX_PORT_BYTES); in t4_get_port_stats()
8737 p->rx_frames += GET_STAT(RX_PORT_FRAMES); in t4_get_port_stats()
8738 p->rx_bcast_frames += GET_STAT(RX_PORT_BCAST); in t4_get_port_stats()
8739 p->rx_mcast_frames += GET_STAT(RX_PORT_MCAST); in t4_get_port_stats()
8740 p->rx_ucast_frames += GET_STAT(RX_PORT_UCAST); in t4_get_port_stats()
8741 p->rx_too_long += GET_STAT(RX_PORT_MTU_ERROR); in t4_get_port_stats()
8742 p->rx_jabber += GET_STAT(RX_PORT_MTU_CRC_ERROR); in t4_get_port_stats()
8743 p->rx_len_err += GET_STAT(RX_PORT_LEN_ERROR); in t4_get_port_stats()
8744 p->rx_symbol_err += GET_STAT(RX_PORT_SYM_ERROR); in t4_get_port_stats()
8745 p->rx_runt += GET_STAT(RX_PORT_LESS_64B); in t4_get_port_stats()
8746 p->rx_frames_64 += GET_STAT(RX_PORT_64B); in t4_get_port_stats()
8747 p->rx_frames_65_127 += GET_STAT(RX_PORT_65B_127B); in t4_get_port_stats()
8748 p->rx_frames_128_255 += GET_STAT(RX_PORT_128B_255B); in t4_get_port_stats()
8749 p->rx_frames_256_511 += GET_STAT(RX_PORT_256B_511B); in t4_get_port_stats()
8750 p->rx_frames_512_1023 += GET_STAT(RX_PORT_512B_1023B); in t4_get_port_stats()
8751 p->rx_frames_1024_1518 += GET_STAT(RX_PORT_1024B_1518B); in t4_get_port_stats()
8752 p->rx_frames_1519_max += GET_STAT(RX_PORT_1519B_MAX); in t4_get_port_stats()
8753 p->rx_ppp0 += GET_STAT(RX_PORT_PPP0); in t4_get_port_stats()
8754 p->rx_ppp1 += GET_STAT(RX_PORT_PPP1); in t4_get_port_stats()
8755 p->rx_ppp2 += GET_STAT(RX_PORT_PPP2); in t4_get_port_stats()
8756 p->rx_ppp3 += GET_STAT(RX_PORT_PPP3); in t4_get_port_stats()
8757 p->rx_ppp4 += GET_STAT(RX_PORT_PPP4); in t4_get_port_stats()
8758 p->rx_ppp5 += GET_STAT(RX_PORT_PPP5); in t4_get_port_stats()
8759 p->rx_ppp6 += GET_STAT(RX_PORT_PPP6); in t4_get_port_stats()
8760 p->rx_ppp7 += GET_STAT(RX_PORT_PPP7); in t4_get_port_stats()
8762 MPASS(pi->fcs_reg == A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L); in t4_get_port_stats()
8763 p->rx_fcs_err += GET_STAT(RX_PORT_CRC_ERROR); in t4_get_port_stats()
8768 if (is_t6(adap) && pi->fcs_reg != -1) in t4_get_port_stats()
8769 p->rx_fcs_err = t4_read_reg64(adap, in t4_get_port_stats()
8770 t4_port_reg(adap, pi->tx_chan, pi->fcs_reg)) - pi->fcs_base; in t4_get_port_stats()
8775 p->tx_frames -= p->tx_pause; in t4_get_port_stats()
8776 p->tx_octets -= p->tx_pause * 64; in t4_get_port_stats()
8779 p->tx_mcast_frames -= p->tx_pause; in t4_get_port_stats()
8781 p->rx_frames -= p->rx_pause; in t4_get_port_stats()
8782 p->rx_octets -= p->rx_pause * 64; in t4_get_port_stats()
8785 p->rx_mcast_frames -= p->rx_pause; in t4_get_port_stats()
8789 bgmap = pi->mps_bg_map; in t4_get_port_stats()
8790 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
8791 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
8792 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
8793 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
8794 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
8795 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
8796 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
8797 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
8802 * t4_get_lb_stats - collect loopback port statistics
8817 p->octets = GET_STAT(BYTES); in t4_get_lb_stats()
8818 p->frames = GET_STAT(FRAMES); in t4_get_lb_stats()
8819 p->bcast_frames = GET_STAT(BCAST); in t4_get_lb_stats()
8820 p->mcast_frames = GET_STAT(MCAST); in t4_get_lb_stats()
8821 p->ucast_frames = GET_STAT(UCAST); in t4_get_lb_stats()
8822 p->error_frames = GET_STAT(ERROR); in t4_get_lb_stats()
8824 p->frames_64 = GET_STAT(64B); in t4_get_lb_stats()
8825 p->frames_65_127 = GET_STAT(65B_127B); in t4_get_lb_stats()
8826 p->frames_128_255 = GET_STAT(128B_255B); in t4_get_lb_stats()
8827 p->frames_256_511 = GET_STAT(256B_511B); in t4_get_lb_stats()
8828 p->frames_512_1023 = GET_STAT(512B_1023B); in t4_get_lb_stats()
8829 p->frames_1024_1518 = GET_STAT(1024B_1518B); in t4_get_lb_stats()
8830 p->frames_1519_max = GET_STAT(1519B_MAX); in t4_get_lb_stats()
8831 p->drop = GET_STAT(DROP_FRAMES); in t4_get_lb_stats()
8833 if (idx < adap->params.nports) { in t4_get_lb_stats()
8834 u32 bg = adap2pinfo(adap, idx)->mps_bg_map; in t4_get_lb_stats()
8836 p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
8837 p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
8838 p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
8839 p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
8840 p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
8841 p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
8842 p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
8843 p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
8851 * t4_wol_magic_enable - enable/disable magic packet WoL
8856 * Enables/disables magic packet wake-on-LAN for the selected port.
8889 * t4_wol_pat_enable - enable/disable pattern-based WoL
8893 * @mask0: byte mask for bytes 0-63 of a packet
8894 * @mask1: byte mask for bytes 64-127 of a packet
8900 * the resulting packet against @crc. If @enable is %true pattern-based
8921 return -EINVAL; in t4_wol_pat_enable()
8940 return -ETIMEDOUT; in t4_wol_pat_enable()
8947 return -ETIMEDOUT; in t4_wol_pat_enable()
8955 /* t4_mk_filtdelwr - create a delete filter WR
8966 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); in t4_mk_filtdelwr()
8967 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); in t4_mk_filtdelwr()
8968 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | in t4_mk_filtdelwr()
8970 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); in t4_mk_filtdelwr()
8972 wr->rx_chan_rx_rpl_iq = in t4_mk_filtdelwr()
9003 * t4_mdio_rd - read a PHY register through MDIO
9037 * t4_mdio_wr - write a PHY register through MDIO
9069 * t4_sge_decode_idma_state - decode the idma state
9226 * t4_sge_ctxt_flush - flush the SGE context cache
9254 * t4_fw_hello - establish communication with FW
9259 * @state: returns the current device state (if non-NULL)
9294 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) in t4_fw_hello()
9314 * Note that we also do this wait if we're a non-Master-capable PF and in t4_fw_hello()
9336 waiting -= 50; in t4_fw_hello()
9347 if (retries-- > 0) in t4_fw_hello()
9350 return -ETIMEDOUT; in t4_fw_hello()
9382 * t4_fw_bye - end communication with FW
9398 * t4_fw_reset - issue a reset to FW
9416 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
9439 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) { in t4_fw_halt()
9476 * t4_fw_restart - restart the firmware by taking the uP out of RESET
9495 return -ETIMEDOUT; in t4_fw_restart()
9499 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
9524 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; in t4_fw_upgrade()
9528 return -EINVAL; in t4_fw_upgrade()
9544 * t4_fw_initialize - ask FW to initialize the device
9561 * t4_query_params_rw - query FW or device parameters
9583 return -EINVAL; in t4_query_params_rw()
9623 * t4_set_params_timeout - sets FW or device parameters
9645 return -EINVAL; in t4_set_params_timeout()
9654 while (nparams--) { in t4_set_params_timeout()
9663 * t4_set_params - sets FW or device parameters
9684 * t4_cfg_pfvf - configure PF/VF resource limits
9691 * @rxqi: the max number of interrupt-capable ingress queues
9732 * t4_alloc_vi_func - allocate a virtual interface
9749 * Returns a negative error number or the non-negative VI id.
9768 c.nmac = nmac - 1; in t4_alloc_vi_func()
9793 *vfvld = adap->params.viid_smt_extn_support ? in t4_alloc_vi_func()
9798 *vin = adap->params.viid_smt_extn_support ? in t4_alloc_vi_func()
9807 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
9830 * t4_free_vi - free a virtual interface
9857 * t4_set_rxmode - set Rx properties of a virtual interface
9861 * @mtu: the new MTU or -1
9862 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
9863 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
9864 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
9865 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
9903 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
9935 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | in t4_alloc_encap_mac_filt()
9937 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_alloc_encap_mac_filt()
9938 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask)); in t4_alloc_encap_mac_filt()
9940 p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) | in t4_alloc_encap_mac_filt()
9943 p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask)); in t4_alloc_encap_mac_filt()
9945 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_alloc_encap_mac_filt()
9947 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); in t4_alloc_encap_mac_filt()
9952 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
9984 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx)); in t4_alloc_raw_mac_filt()
9987 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | in t4_alloc_raw_mac_filt()
9990 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | in t4_alloc_raw_mac_filt()
9994 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); in t4_alloc_raw_mac_filt()
9995 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); in t4_alloc_raw_mac_filt()
9997 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_alloc_raw_mac_filt()
9999 ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd)); in t4_alloc_raw_mac_filt()
10001 ret = -ENOMEM; in t4_alloc_raw_mac_filt()
10008 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
10019 * Allocates an exact-match filter for each of the supplied addresses and
10036 unsigned int max_naddr = adap->chip_params->mps_tcam_size; in t4_alloc_mac_filt()
10040 return -EINVAL; in t4_alloc_mac_filt()
10061 p->valid_to_idx = in t4_alloc_mac_filt()
10064 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); in t4_alloc_mac_filt()
10073 if (ret && ret != -FW_ENOMEM) in t4_alloc_mac_filt()
10078 be16_to_cpu(p->valid_to_idx)); in t4_alloc_mac_filt()
10092 rem -= fw_naddr; in t4_alloc_mac_filt()
10095 if (ret == 0 || ret == -FW_ENOMEM) in t4_alloc_mac_filt()
10101 * t4_free_encap_mac_filt - frees MPS entry at given index
10131 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | in t4_free_encap_mac_filt()
10133 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_free_encap_mac_filt()
10135 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_free_encap_mac_filt()
10140 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
10172 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) | in t4_free_raw_mac_filt()
10176 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | in t4_free_raw_mac_filt()
10179 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | in t4_free_raw_mac_filt()
10183 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); in t4_free_raw_mac_filt()
10184 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); in t4_free_raw_mac_filt()
10186 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_free_raw_mac_filt()
10190 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
10198 * Frees the exact-match filter for each of the supplied addresses
10209 unsigned int max_naddr = adap->chip_params->mps_tcam_size; in t4_free_mac_filt()
10213 return -EINVAL; in t4_free_mac_filt()
10235 p->valid_to_idx = cpu_to_be16( in t4_free_mac_filt()
10238 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); in t4_free_mac_filt()
10247 be16_to_cpu(p->valid_to_idx)); in t4_free_mac_filt()
10254 rem -= fw_naddr; in t4_free_mac_filt()
10263 * t4_change_mac - modifies the exact-match filter for a MAC address
10267 * @idx: index of existing filter for old value of MAC address, or -1
10272 * Modifies an exact-match filter and sets it to the new MAC address if
10290 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; in t4_change_mac()
10301 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | in t4_change_mac()
10304 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_change_mac()
10308 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); in t4_change_mac()
10310 ret = -ENOMEM; in t4_change_mac()
10312 if (adap->params.viid_smt_extn_support) in t4_change_mac()
10326 * t4_set_addr_hash - program the MAC inexact-match hash filter
10334 * Sets the 64-bit inexact-match hash filter for a virtual interface.
10354 * t4_enable_vi_params - enable/disable a virtual interface
10382 * t4_enable_vi - enable/disable a virtual interface
10399 * t4_identify_port - identify a VI's port by blinking its LED
10422 * t4_iq_stop - stop an ingress queue and its FLs
10455 * t4_iq_free - free an ingress queue and its FLs
10486 * t4_eth_eq_stop - stop an Ethernet egress queue
10512 * t4_eth_eq_free - free an Ethernet egress queue
10537 * t4_ctrl_eq_free - free a control egress queue
10562 * t4_ofld_eq_free - free an offload egress queue
10587 * t4_link_down_rc_str - return a string for a Link Down Reason Code
10597 "Auto-negotiation Failure", in t4_link_down_rc_str()
10690 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
10694 * 32-bit Port Capabilities value.
10702 * 16-bit Port Information message isn't the same as the in lstatus_to_fwcap()
10703 * 16-bit Port Capabilities bitfield used everywhere else ... in lstatus_to_fwcap()
10733 struct link_config old_lc, *lc = &pi->link_cfg; in handle_port_info()
10738 old_ptype = pi->port_type; in handle_port_info()
10739 old_mtype = pi->mod_type; in handle_port_info()
10742 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); in handle_port_info()
10744 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); in handle_port_info()
10745 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); in handle_port_info()
10746 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? in handle_port_info()
10747 G_FW_PORT_CMD_MDIOADDR(stat) : -1; in handle_port_info()
10749 lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap)); in handle_port_info()
10750 lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap)); in handle_port_info()
10751 lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap)); in handle_port_info()
10752 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; in handle_port_info()
10753 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); in handle_port_info()
10757 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32); in handle_port_info()
10759 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat); in handle_port_info()
10760 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat); in handle_port_info()
10761 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ? in handle_port_info()
10762 G_FW_PORT_CMD_MDIOADDR32(stat) : -1; in handle_port_info()
10764 lc->pcaps = be32_to_cpu(p->u.info32.pcaps32); in handle_port_info()
10765 lc->acaps = be32_to_cpu(p->u.info32.acaps32); in handle_port_info()
10766 lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32); in handle_port_info()
10767 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; in handle_port_info()
10768 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat); in handle_port_info()
10770 linkattr = be32_to_cpu(p->u.info32.linkattr32); in handle_port_info()
10772 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); in handle_port_info()
10776 lc->speed = fwcap_to_speed(linkattr); in handle_port_info()
10777 lc->fec = fwcap_to_fec(linkattr, true); in handle_port_info()
10784 lc->fc = fc; in handle_port_info()
10790 if (old_ptype != pi->port_type || old_mtype != pi->mod_type || in handle_port_info()
10791 old_lc.pcaps != lc->pcaps) { in handle_port_info()
10792 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) in handle_port_info()
10793 lc->fec_hint = fwcap_to_fec(lc->acaps, true); in handle_port_info()
10797 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed || in handle_port_info()
10798 old_lc.fec != lc->fec || old_lc.fc != lc->fc) { in handle_port_info()
10805 * t4_update_port_info - retrieve and update port information if changed
10814 struct adapter *sc = pi->adapter; in t4_update_port_info()
10822 V_FW_PORT_CMD_PORTID(pi->hw_port)); in t4_update_port_info()
10823 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 : in t4_update_port_info()
10827 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); in t4_update_port_info()
10836 * t4_handle_fw_rpl - process a FW reply message
10847 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); in t4_handle_fw_rpl()
10854 int hw_port = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); in t4_handle_fw_rpl()
10855 int port_id = adap->port_map[hw_port]; in t4_handle_fw_rpl()
10858 MPASS(port_id >= 0 && port_id < adap->params.nports); in t4_handle_fw_rpl()
10859 pi = adap->port[port_id]; in t4_handle_fw_rpl()
10872 return -EINVAL; in t4_handle_fw_rpl()
10878 * get_pci_mode - determine a card's PCI mode
10894 p->speed = val & PCI_EXP_LNKSTA_CLS; in get_pci_mode()
10895 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; in get_pci_mode()
10907 * Table for non-standard supported Flash parts. Note, all Flash in t4_get_flash_params()
10934 * Check to see if it's one of our non-standard supported Flash parts. in t4_get_flash_params()
10938 adapter->params.sf_size = in t4_get_flash_params()
10940 adapter->params.sf_nsec = in t4_get_flash_params()
10941 adapter->params.sf_size / SF_SEC_SIZE; in t4_get_flash_params()
10958 * This Density -> Size decoding table is taken from Micron in t4_get_flash_params()
10975 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ in t4_get_flash_params()
10977 * This Density -> Size decoding table is taken from ISSI in t4_get_flash_params()
10989 * This Density -> Size decoding table is taken from Macronix in t4_get_flash_params()
11001 * This Density -> Size decoding table is taken from Winbond in t4_get_flash_params()
11027 adapter->params.sf_size = size; in t4_get_flash_params()
11028 adapter->params.sf_nsec = size / SF_SEC_SIZE; in t4_get_flash_params()
11036 if (adapter->params.sf_size < FLASH_MIN_SIZE) in t4_get_flash_params()
11038 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); in t4_get_flash_params()
11135 chipid -= CHELSIO_T4; in t4_get_chip_params()
11143 * t4_prep_adapter - prepare SW and HW for operation
11157 get_pci_mode(adapter, &adapter->params.pci); in t4_prep_adapter()
11160 adapter->params.chipid = G_CHIPID(pl_rev); in t4_prep_adapter()
11161 adapter->params.rev = G_REV(pl_rev); in t4_prep_adapter()
11162 if (adapter->params.chipid == 0) { in t4_prep_adapter()
11164 adapter->params.chipid = CHELSIO_T4; in t4_prep_adapter()
11167 if (adapter->params.rev == 1) { in t4_prep_adapter()
11169 return -EINVAL; in t4_prep_adapter()
11173 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); in t4_prep_adapter()
11174 if (adapter->chip_params == NULL) in t4_prep_adapter()
11175 return -EINVAL; in t4_prep_adapter()
11177 adapter->params.pci.vpd_cap_addr = in t4_prep_adapter()
11187 adapter->params.cim_la_size = adapter->chip_params->cim_la_size; in t4_prep_adapter()
11190 adapter->params.fpga = 1; in t4_prep_adapter()
11191 adapter->params.cim_la_size = 2 * adapter->chip_params->cim_la_size; in t4_prep_adapter()
11194 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf); in t4_prep_adapter()
11198 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); in t4_prep_adapter()
11203 adapter->params.nports = 1; in t4_prep_adapter()
11204 adapter->params.portvec = 1; in t4_prep_adapter()
11205 adapter->params.vpd.cclk = 50000; in t4_prep_adapter()
11213 * t4_shutdown_adapter - shut down adapter, host & wire
11221 * the port Link Status to go down -- if register writes work --
11227 const bool bt = adapter->bt_map != 0; in t4_shutdown_adapter()
11256 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
11296 return -EINVAL; in t4_bar2_sge_qregs()
11300 page_shift = adapter->params.sge.page_shift; in t4_bar2_sge_qregs()
11306 ? adapter->params.sge.eq_s_qpp in t4_bar2_sge_qregs()
11307 : adapter->params.sge.iq_s_qpp); in t4_bar2_sge_qregs()
11308 qpp_mask = (1 << qpp_shift) - 1; in t4_bar2_sge_qregs()
11330 * from the writes to the registers -- the Write Combined Doorbell in t4_bar2_sge_qregs()
11348 * t4_init_devlog_ncores_params - initialize adap->params.devlog and ncores
11354 struct devlog_params *dparams = &adap->params.devlog; in t4_init_devlog_ncores_params()
11371 adap->params.ncores = 1 << ncore_shift; in t4_init_devlog_ncores_params()
11373 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); in t4_init_devlog_ncores_params()
11374 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; in t4_init_devlog_ncores_params()
11377 dparams->size = nentries * sizeof(struct fw_devlog_e); in t4_init_devlog_ncores_params()
11385 adap->params.ncores = 1; in t4_init_devlog_ncores_params()
11393 return -ENXIO; in t4_init_devlog_ncores_params()
11401 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), in t4_init_devlog_ncores_params()
11408 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); in t4_init_devlog_ncores_params()
11409 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; in t4_init_devlog_ncores_params()
11410 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); in t4_init_devlog_ncores_params()
11416 * t4_init_sge_params - initialize adap->params.sge
11424 struct sge_params *sp = &adapter->params.sge; in t4_init_sge_params()
11428 sp->counter_val[0] = G_THRESHOLD_0(r); in t4_init_sge_params()
11429 sp->counter_val[1] = G_THRESHOLD_1(r); in t4_init_sge_params()
11430 sp->counter_val[2] = G_THRESHOLD_2(r); in t4_init_sge_params()
11431 sp->counter_val[3] = G_THRESHOLD_3(r); in t4_init_sge_params()
11443 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; in t4_init_sge_params()
11444 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; in t4_init_sge_params()
11446 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; in t4_init_sge_params()
11447 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; in t4_init_sge_params()
11449 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; in t4_init_sge_params()
11450 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; in t4_init_sge_params()
11453 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; in t4_init_sge_params()
11455 sp->fl_starve_threshold2 = sp->fl_starve_threshold; in t4_init_sge_params()
11457 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; in t4_init_sge_params()
11459 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; in t4_init_sge_params()
11464 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; in t4_init_sge_params()
11465 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; in t4_init_sge_params()
11470 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; in t4_init_sge_params()
11471 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; in t4_init_sge_params()
11475 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; in t4_init_sge_params()
11476 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; in t4_init_sge_params()
11479 sp->sge_control = r; in t4_init_sge_params()
11480 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; in t4_init_sge_params()
11481 sp->fl_pktshift = G_PKTSHIFT(r); in t4_init_sge_params()
11483 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + in t4_init_sge_params()
11486 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + in t4_init_sge_params()
11490 sp->pack_boundary = sp->pad_boundary; in t4_init_sge_params()
11494 sp->pack_boundary = 16; in t4_init_sge_params()
11496 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); in t4_init_sge_params()
11499 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, in t4_init_sge_params()
11525 mask = (1 << t4_filter_field_width(adap, i)) - 1; in hashmask_to_filtermask()
11542 struct tp_params *tpp = &adap->params.tp; in read_filter_mode_and_ingress_config()
11551 rc = -t4_query_params(adap, adap->mbox, adap->pf, 0, 2, param, val); in read_filter_mode_and_ingress_config()
11553 tpp->filter_mode = G_FW_PARAMS_PARAM_FILTER_MODE(val[0]); in read_filter_mode_and_ingress_config()
11554 tpp->filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val[0]); in read_filter_mode_and_ingress_config()
11555 tpp->vnic_mode = val[1]; in read_filter_mode_and_ingress_config()
11562 tpp->filter_mode = v & 0xffff; in read_filter_mode_and_ingress_config()
11579 tpp->filter_mask = hashmask_to_filtermask(adap, hash_mask, in read_filter_mode_and_ingress_config()
11580 tpp->filter_mode); in read_filter_mode_and_ingress_config()
11584 tpp->vnic_mode = FW_VNIC_MODE_PF_VF; in read_filter_mode_and_ingress_config()
11586 tpp->vnic_mode = FW_VNIC_MODE_OUTER_VLAN; in read_filter_mode_and_ingress_config()
11595 tpp->ipsecidx_shift = t4_filter_field_shift(adap, F_IPSECIDX); in read_filter_mode_and_ingress_config()
11596 tpp->fcoe_shift = t4_filter_field_shift(adap, F_T7_FCOE); in read_filter_mode_and_ingress_config()
11597 tpp->port_shift = t4_filter_field_shift(adap, F_T7_PORT); in read_filter_mode_and_ingress_config()
11598 tpp->vnic_shift = t4_filter_field_shift(adap, F_T7_VNIC_ID); in read_filter_mode_and_ingress_config()
11599 tpp->vlan_shift = t4_filter_field_shift(adap, F_T7_VLAN); in read_filter_mode_and_ingress_config()
11600 tpp->tos_shift = t4_filter_field_shift(adap, F_T7_TOS); in read_filter_mode_and_ingress_config()
11601 tpp->protocol_shift = t4_filter_field_shift(adap, F_T7_PROTOCOL); in read_filter_mode_and_ingress_config()
11602 tpp->ethertype_shift = t4_filter_field_shift(adap, F_T7_ETHERTYPE); in read_filter_mode_and_ingress_config()
11603 tpp->macmatch_shift = t4_filter_field_shift(adap, F_T7_MACMATCH); in read_filter_mode_and_ingress_config()
11604 tpp->matchtype_shift = t4_filter_field_shift(adap, F_T7_MPSHITTYPE); in read_filter_mode_and_ingress_config()
11605 tpp->frag_shift = t4_filter_field_shift(adap, F_T7_FRAGMENTATION); in read_filter_mode_and_ingress_config()
11606 tpp->roce_shift = t4_filter_field_shift(adap, F_ROCE); in read_filter_mode_and_ingress_config()
11607 tpp->synonly_shift = t4_filter_field_shift(adap, F_SYNONLY); in read_filter_mode_and_ingress_config()
11608 tpp->tcpflags_shift = t4_filter_field_shift(adap, F_TCPFLAGS); in read_filter_mode_and_ingress_config()
11610 tpp->ipsecidx_shift = -1; in read_filter_mode_and_ingress_config()
11611 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); in read_filter_mode_and_ingress_config()
11612 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); in read_filter_mode_and_ingress_config()
11613 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); in read_filter_mode_and_ingress_config()
11614 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); in read_filter_mode_and_ingress_config()
11615 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); in read_filter_mode_and_ingress_config()
11616 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); in read_filter_mode_and_ingress_config()
11617 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); in read_filter_mode_and_ingress_config()
11618 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); in read_filter_mode_and_ingress_config()
11619 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); in read_filter_mode_and_ingress_config()
11620 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); in read_filter_mode_and_ingress_config()
11621 tpp->roce_shift = -1; in read_filter_mode_and_ingress_config()
11622 tpp->synonly_shift = -1; in read_filter_mode_and_ingress_config()
11623 tpp->tcpflags_shift = -1; in read_filter_mode_and_ingress_config()
11628 * t4_init_tp_params - initialize adap->params.tp
11636 struct tp_params *tpp = &adap->params.tp; in t4_init_tp_params()
11639 tpp->tre = G_TIMERRESOLUTION(v); in t4_init_tp_params()
11640 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); in t4_init_tp_params()
11644 tpp->rx_pkt_encap = false; in t4_init_tp_params()
11645 tpp->lb_mode = 0; in t4_init_tp_params()
11646 tpp->lb_nchan = 1; in t4_init_tp_params()
11649 tpp->rx_pkt_encap = v & F_CRXPKTENC; in t4_init_tp_params()
11652 tpp->lb_mode = G_T7_LB_MODE(v); in t4_init_tp_params()
11653 if (tpp->lb_mode == 1) in t4_init_tp_params()
11654 tpp->lb_nchan = 4; in t4_init_tp_params()
11655 else if (tpp->lb_mode == 2) in t4_init_tp_params()
11656 tpp->lb_nchan = 2; in t4_init_tp_params()
11672 tpp->max_tx_pdu = tx_len; in t4_init_tp_params()
11673 tpp->max_rx_pdu = rx_len; in t4_init_tp_params()
11679 * t4_filter_field_width - returns the width of a filter field
11689 const int nopt = adap->chip_params->filter_num_opt; in t4_filter_field_width()
11726 * t4_filter_field_shift - calculate filter field shift
11736 const unsigned int filter_mode = adap->params.tp.filter_mode; in t4_filter_field_shift()
11741 return -1; in t4_filter_field_shift()
11836 struct vi_info *vi = &p->vi[0]; in t4_port_init()
11838 for (i = 0, j = -1; i <= p->port_id; i++) { in t4_port_init()
11841 } while ((adap->params.portvec & (1 << j)) == 0); in t4_port_init()
11844 p->hw_port = j; in t4_port_init()
11845 p->tx_chan = t4_get_tx_c_chan(adap, j); in t4_port_init()
11846 p->rx_chan = t4_get_rx_c_chan(adap, j); in t4_port_init()
11847 p->mps_bg_map = t4_get_mps_bg_map(adap, j); in t4_port_init()
11848 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); in t4_port_init()
11850 if (!(adap->flags & IS_VF) || in t4_port_init()
11851 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { in t4_port_init()
11855 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size, in t4_port_init()
11856 &vi->vfvld, &vi->vin); in t4_port_init()
11860 vi->viid = ret; in t4_port_init()
11865 V_FW_PARAMS_PARAM_YZ(vi->viid); in t4_port_init()
11868 vi->rss_base = 0xffff; in t4_port_init()
11871 vi->rss_base = val & 0xffff; in t4_port_init()
11885 /* value is in 512-byte units */ in t4_read_cimq_cfg_ibq_core()
11889 /* value is in 256-byte units */ in t4_read_cimq_cfg_ibq_core()
11900 *thres = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ in t4_read_cimq_cfg_ibq_core()
11911 /* value is in 512-byte units */ in t4_read_cimq_cfg_obq_core()
11915 /* value is in 256-byte units */ in t4_read_cimq_cfg_obq_core()
11928 * t4_read_cimq_cfg_core - read CIM queue configuration on specific core
11941 unsigned int cim_num_ibq = adap->chip_params->cim_num_ibq; in t4_read_cimq_cfg_core()
11942 unsigned int cim_num_obq = adap->chip_params->cim_num_obq; in t4_read_cimq_cfg_core()
11958 /* It might take 3-10ms before the IBQ debug read access is allowed. in t4_read_cim_ibq_data_core()
11979 * t4_read_cim_ibq_core - read the contents of a CIM inbound queue on
11985 * @n: capacity of @data in 32-bit words
11989 * of 4. Returns < 0 on error and the number of 32-bit words actually
11995 unsigned int cim_num_ibq = adap->chip_params->cim_num_ibq; in t4_read_cim_ibq_core()
11999 if (qid > (cim_num_ibq - 1) || (n & 3)) in t4_read_cim_ibq_core()
12000 return -EINVAL; in t4_read_cim_ibq_core()
12039 * t4_read_cim_obq_core - read the contents of a CIM outbound queue on
12045 * @n: capacity of @data in 32-bit words
12049 * of 4. Returns < 0 on error and the number of 32-bit words actually
12055 unsigned int cim_num_obq = adap->chip_params->cim_num_obq; in t4_read_cim_obq_core()
12059 if ((qid > (cim_num_obq - 1)) || (n & 3)) in t4_read_cim_obq_core()
12060 return -EINVAL; in t4_read_cim_obq_core()
12079 * t4_cim_read_core - read a block from CIM internal address space
12088 * Reads a block of 4-byte words from the CIM intenal address space
12106 return -EBUSY; in t4_cim_read_core()
12108 for ( ; !ret && n--; addr += 4) { in t4_cim_read_core()
12120 * t4_cim_write_core - write a block into CIM internal address space
12129 * Writes a block of 4-byte words into the CIM intenal address space
12149 return -EBUSY; in t4_cim_write_core()
12151 for ( ; !ret && n--; addr += 4) { in t4_cim_write_core()
12162 * t4_cim_read_la_core - read CIM LA capture buffer on specific core
12199 for (i = 0; i < adap->params.cim_la_size; i++) { in t4_cim_read_la_core()
12210 ret = -ETIMEDOUT; in t4_cim_read_la_core()
12218 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to in t4_cim_read_la_core()
12219 * identify the 32-bit portion of the full 312-bit data in t4_cim_read_la_core()
12243 * t4_tp_read_la - read TP LA capture buffer
12260 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); in t4_tp_read_la()
12272 val |= adap->params.tp.la_mask; in t4_tp_read_la()
12282 la_buf[TPLA_SIZE - 1] = ~0ULL; in t4_tp_read_la()
12286 cfg | adap->params.tp.la_mask); in t4_tp_read_la()
12301 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
12322 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ in t4_idma_monitor_init()
12323 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; in t4_idma_monitor_init()
12327 * t4_idma_monitor - monitor SGE Ingress DMA state
12359 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { in t4_idma_monitor()
12360 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) in t4_idma_monitor()
12363 i, idma->idma_qid[i], in t4_idma_monitor()
12364 idma->idma_stalled[i]/hz); in t4_idma_monitor()
12365 idma->idma_stalled[i] = 0; in t4_idma_monitor()
12378 if (idma->idma_stalled[i] == 0) { in t4_idma_monitor()
12379 idma->idma_stalled[i] = hz; in t4_idma_monitor()
12380 idma->idma_warn[i] = 0; in t4_idma_monitor()
12382 idma->idma_stalled[i] += ticks; in t4_idma_monitor()
12383 idma->idma_warn[i] -= ticks; in t4_idma_monitor()
12386 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) in t4_idma_monitor()
12391 if (idma->idma_warn[i] > 0) in t4_idma_monitor()
12393 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; in t4_idma_monitor()
12401 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; in t4_idma_monitor()
12405 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; in t4_idma_monitor()
12409 i, idma->idma_qid[i], idma->idma_state[i], in t4_idma_monitor()
12410 idma->idma_stalled[i]/hz, in t4_idma_monitor()
12412 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); in t4_idma_monitor()
12417 * t4_set_vf_mac - Set MAC address for the specified VF
12455 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd); in t4_set_vf_mac()
12459 * t4_read_pace_tbl - read the pace table
12477 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
12491 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; in t4_get_tx_sched()
12500 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ in t4_get_tx_sched()
12505 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; in t4_get_tx_sched()
12515 * t4_load_cfg - download config file
12534 return -EFBIG; in t4_load_cfg()
12540 flash_cfg_start_sec + i - 1); in t4_load_cfg()
12543 * with the on-adapter Firmware Configuration File. in t4_load_cfg()
12551 n = min(size - i, SF_PAGE_SIZE); in t4_load_cfg()
12567 * t5_fw_init_extern_mem - initialize the external memory
12583 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, in t5_fw_init_extern_mem()
12618 * 0x2-0xFFFF: Reserved
12639 * 0x00: Intel IA-32, PC-AT compatible. Legacy
12641 * 0x02: Hewlett-Packard PA RISC. HP reserved
12643 * 0x04-0xFF: Reserved.
12661 * modify_device_id - Modifies the device ID of the Boot BIOS image
12679 le16_to_cpu(*(u16*)header->pcir_offset)]; in modify_device_id()
12686 * 0x04-0xFF: Do not modify in modify_device_id()
12688 if (pcir_header->code_type == 0x00) { in modify_device_id()
12695 *(u16*) pcir_header->device_id = device_id; in modify_device_id()
12701 header->cksum = 0x0; in modify_device_id()
12706 for (i = 0; i < (header->size512 * 512); i++) in modify_device_id()
12713 boot_data[cur_header + 7] = -csum; in modify_device_id()
12715 } else if (pcir_header->code_type == 0x03) { in modify_device_id()
12720 *(u16*) pcir_header->device_id = device_id; in modify_device_id()
12729 if (pcir_header->indicator & 0x80) in modify_device_id()
12735 cur_header += header->size512 * 512; in modify_device_id()
12740 * t4_load_boot - download boot flash
12747 * The boot image has the following sections: a 28-byte header and the
12768 return -EFBIG; in t4_load_boot()
12772 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, in t4_load_boot()
12778 (boot_sector >> 16) + i - 1); in t4_load_boot()
12782 * with the on-adapter option ROM file in t4_load_boot()
12789 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); in t4_load_boot()
12800 return -EFBIG; in t4_load_boot()
12807 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { in t4_load_boot()
12809 return -EINVAL; in t4_load_boot()
12815 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { in t4_load_boot()
12817 return -EINVAL; in t4_load_boot()
12823 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { in t4_load_boot()
12825 return -EINVAL; in t4_load_boot()
12839 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { in t4_load_boot()
12854 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { in t4_load_boot()
12872 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
12888 if (adapter->params.sf_size < start + len) in t4_flash_bootcfg_addr()
12889 return -ENOSPC; in t4_flash_bootcfg_addr()
12907 return -EFBIG; in t4_load_bootcfg()
12913 flash_cfg_start_sec + i - 1); in t4_load_bootcfg()
12917 * with the on-adapter OptionROM Configuration File. in t4_load_bootcfg()
12925 n = min(size - i, SF_PAGE_SIZE); in t4_load_bootcfg()
12941 * t4_set_filter_cfg - set up filter mode/mask and ingress config.
12957 const int maxbits = adap->chip_params->filter_opt_len; in t4_set_filter_cfg()
12958 const int nopt = adap->chip_params->filter_num_opt; in t4_set_filter_cfg()
12961 if (mode != -1 || mask != -1) { in t4_set_filter_cfg()
12962 if (mode != -1) { in t4_set_filter_cfg()
12974 return -E2BIG; in t4_set_filter_cfg()
12995 fmask = fmode & adap->params.tp.filter_mask; in t4_set_filter_cfg()
12996 if (fmask != adap->params.tp.filter_mask) { in t4_set_filter_cfg()
13000 adap->params.tp.filter_mask, fmask, fmode); in t4_set_filter_cfg()
13003 fmode = adap->params.tp.filter_mode; in t4_set_filter_cfg()
13009 return -EINVAL; in t4_set_filter_cfg()
13018 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, in t4_set_filter_cfg()
13024 if (vnic_mode != -1) { in t4_set_filter_cfg()
13029 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, in t4_set_filter_cfg()
13042 * t4_clr_port_stats - clear port statistics
13054 port_id = adap->port_map[idx]; in t4_clr_port_stats()
13055 MPASS(port_id >= 0 && port_id <= adap->params.nports); in t4_clr_port_stats()
13056 pi = adap->port[port_id]; in t4_clr_port_stats()
13058 for (tx_chan = pi->tx_chan; in t4_clr_port_stats()
13059 tx_chan < pi->tx_chan + adap->params.tp.lb_nchan; tx_chan++) { in t4_clr_port_stats()
13069 bgmap = pi->mps_bg_map; in t4_clr_port_stats()
13080 * t4_i2c_io - read/write I2C data from adapter
13082 * @port: Port number if per-port device; <0 if not
13083 * @devid: per-port device ID or absolute device ID
13101 return -EINVAL; in t4_i2c_io()
13105 return -EINVAL; in t4_i2c_io()
13135 len -= i2c_len; in t4_i2c_io()
13158 * t4_sge_ctxt_rd - read an SGE context through FW
13204 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
13244 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), in t4_sched_config()
13275 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), in t4_sched_params()
13297 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), in t4_sched_params_ch_rl()
13307 return -EINVAL; in t4_sched_params_cl_wrr()
13322 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), in t4_sched_params_cl_wrr()
13348 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), in t4_sched_params_cl_rl_kbps()
13353 * t4_config_watchdog - configure (enable/disable) a watchdog timer
13362 * action. Configure one of the watchdog timers by setting a non-zero
13375 * "tick" if the timeout is non-zero but the conversion results in 0 in t4_config_watchdog()
13404 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, in t4_get_devlog_level()
13423 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, in t4_set_devlog_level()
13432 adap->params.smac_add_support = 0; in t4_configure_add_smac()
13441 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); in t4_configure_add_smac()
13446 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, in t4_configure_add_smac()
13452 adap->params.smac_add_support = 1; in t4_configure_add_smac()
13470 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); in t4_configure_ringbb()
13482 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); in t4_configure_ringbb()
13494 * t4_set_vlan_acl - Set a VLAN id for the specified VF
13527 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL); in t4_set_vlan_acl()
13531 * t4_del_mac - Removes the exact-match filter for a MAC address
13538 * Modifies an exact-match filter and sets it to the new MAC address if
13551 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; in t4_del_mac()
13561 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_del_mac()
13562 p->valid_to_idx = cpu_to_be16( in t4_del_mac()
13568 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); in t4_del_mac()
13570 return -ENOMEM; in t4_del_mac()
13577 * t4_add_mac - Adds an exact-match filter for a MAC address
13581 * @idx: index of existing filter for old value of MAC address, or -1
13587 * Modifies an exact-match filter and sets it to the new MAC address if
13600 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; in t4_add_mac()
13613 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | in t4_add_mac()
13616 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_add_mac()
13620 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); in t4_add_mac()
13622 return -ENOMEM; in t4_add_mac()
13625 if (adap->params.viid_smt_extn_support) in t4_add_mac()