Lines Matching +full:24 +full:m
189 CCU_GATE(CLK_DRAM_DE_FE1, "dram-de_fe1", "pll_ddr", 0x100, 24)
204 0, 2, 0, 0, /* m factor */
215 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
235 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
264 0, 2, 0, 0, /* m factor */
273 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* m factor */
283 AW_CLK_FACTOR_ZERO_IS_ONE, /* m factor */
293 0, 5, 0, 0, /* m factor */
294 24, 2, /* mux */
304 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
315 0, 2, 0, 0, /* m factor */
327 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
347 0, 2, 0, 0, /* m factor */
359 0, 4, 0, 0, /* m factor */
360 24, 2, /* mux */
369 0, 4, 0, 0, /* m factor */
370 24, 2, /* mux */
379 0, 4, 0, 0, /* m factor */
380 24, 2, /* mux */
390 0, 4, 0, 0, /* m factor */
391 24, 2, /* mux */
401 0, 4, 0, 0, /* m factor */
402 24, 2, /* mux */
412 0, 4, 0, 0, /* m factor */
413 24, 2, /* mux */
423 0, 4, 0, 0, /* m factor */
424 24, 2, /* mux */
433 0, 4, 0, 0, /* m factor */
434 24, 2, /* mux */
443 0, 4, 0, 0, /* m factor */
444 24, 2, /* mux */
453 0, 4, 0, 0, /* m factor */
454 24, 2, /* mux */
463 0, 4, 0, 0, /* m factor */
464 24, 2, /* mux */
475 0, 4, 0, 0, /* m factor */
476 24, 2, /* mux */
485 0, 4, 0, 0, /* m factor */
486 24, 2, /* mux */
498 0, 5, 0, 0, /* m factor */
499 24, 2, /* mux */
509 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
510 24, 1, /* mux */
519 0, 4, 0, 0, /* m factor */
520 24, 2, /* mux */