Lines Matching +full:use +full:- +full:dma +full:- +full:tx

1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
8 * Redistribution and use in source and binary forms, with or without
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: FreeBSD: if_gemvar.h 177560 2008-03-24 17:23:53Z marius
43 * Transmit descriptor ring size - this is arbitrary, but allocate
47 * is however used as an estimate for the TX window size.
53 #define CAS_MAXTXFREE (CAS_NTXDESC - 1)
54 #define CAS_NTXDESC_MASK (CAS_NTXDESC - 1)
58 * Receive completion ring size - we have one completion per
63 #define CAS_NRXCOMP_MASK (CAS_NRXCOMP - 1)
67 * Receive descriptor ring sizes - for Cassini+ and Saturn both
71 #define CAS_NRXDESC_MASK (CAS_NRXDESC - 1)
74 #define CAS_NRXDESC2_MASK (CAS_NRXDESC2 - 1)
84 * Control structures are DMA'd to the chip. We allocate them
85 * in a single clump that maps to a single DMA segment to make
89 struct cas_desc ccd_txdescs[CAS_NTXDESC]; /* TX descriptors */
106 bus_dmamap_t txs_dmamap; /* our DMA map */
120 bus_dmamap_t rxds_dmamap; /* our DMA map */
147 bus_dma_tag_t sc_pdmatag; /* parent bus DMA tag */
148 bus_dma_tag_t sc_rdmatag; /* RX bus DMA tag */
149 bus_dma_tag_t sc_tdmatag; /* TX bus DMA tag */
150 bus_dma_tag_t sc_cdmatag; /* control data bus DMA tag */
151 bus_dmamap_t sc_dmamap; /* bus DMA handle */
161 #define CAS_NO_CSUM (1 << 1) /* don't use hardware checksumming */
164 #define CAS_SERDES (1 << 4) /* use the SERDES */
167 bus_dmamap_t sc_cddmamap; /* control data DMA map */
180 #define sc_txdescs sc_control_data->ccd_txdescs
181 #define sc_rxcomps sc_control_data->ccd_rxcomps
182 #define sc_rxdescs sc_control_data->ccd_rxdescs
183 #define sc_rxdescs2 sc_control_data->ccd_rxdescs2
185 u_int sc_txfree; /* number of free TX descriptors */
186 u_int sc_txnext; /* next ready TX descriptor */
187 u_int sc_txwin; /* TX desc. since last TX intr. */
189 struct cas_txsq sc_txfreeq; /* free software TX descriptors */
190 struct cas_txsq sc_txdirtyq; /* dirty software TX descriptors */
201 bus_barrier((sc)->sc_res[CAS_RES_MEM], (offs), (len), (flags))
204 bus_read_ ## n((sc)->sc_res[CAS_RES_MEM], (offs))
210 bus_write_ ## n((sc)->sc_res[CAS_RES_MEM], (offs), (v))
215 #define CAS_CDTXDADDR(sc, x) ((sc)->sc_cddma + CAS_CDTXDOFF((x)))
216 #define CAS_CDRXCADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXCOFF((x)))
217 #define CAS_CDRXDADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXDOFF((x)))
218 #define CAS_CDRXD2ADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXD2OFF((x)))
221 bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops));
226 refcount_init(&(rxds)->rxds_refcount, 1); \
227 (rxd)->cd_buf_ptr = htole64((rxds)->rxds_paddr); \
230 (rxd)->cd_flags = \
235 __CAS_UPDATE_RXDESC(&(sc)->sc_rxdescs[(d)], \
236 &(sc)->sc_rxdsoft[(s)], (s))
241 mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
242 #define CAS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
243 #define CAS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
244 #define CAS_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what))
245 #define CAS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
246 #define CAS_LOCK_OWNED(_sc) mtx_owned(&(_sc)->sc_mtx)