Lines Matching +full:codec +full:- +full:analog +full:- +full:controls
1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 1999-2015, Broadcom Corporation
9 * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's
30 * JEDEC JEP-106 Core Vendor IDs
32 * These are the JEDEC JEP-106 manufacturer ID representions (with ARM's
33 * non-standard 4-bit continutation code), as used in ARM's PrimeCell
38 * will need to convert bus-specific vendor IDs to their BHND_MFGID
39 * JEP-106 equivalents.
41 * @par ARM 4-bit Continuation Code
43 * BHND MFGIDs are encoded using ARM's non-standard 4-bit continuation code
51 * The 4-bit continuation code field specifies the number of JEP-106
53 * ARM's JEP-106 ID of `0x7F 0x7F 0x7F 0x7F 0x3B`, the four 0x7F continuations
54 * are encoded as '4' in the 4-bit continuation code field (i.e. 0x43B).
56 #define BHND_MFGID_ARM 0x043b /**< arm JEP-106 vendor id */
57 #define BHND_MFGID_BCM 0x04bf /**< broadcom JEP-106 vendor id */
58 #define BHND_MFGID_MIPS 0x04a7 /**< mips JEP-106 vendor id */
59 #define BHND_MFGID_INVALID 0x0000 /**< invalid JEP-106 vendor id */
64 * OCP-IP assigned vendor codes are used by siba(4)
146 #define PCI_DEVID_BCM4306_V90 0x4323 /* 4306 v90 codec */
253 #define PCI_SUBDEVID_BCM4402_V90 0x4403 /* 4402 v90 codec */
260 #define PCI_SUBDEVID_BCM47XX_AUDIO 0x4711 /* 47xx audio codec */
261 #define PCI_SUBDEVID_BCM47XX_V90 0x4712 /* 47xx v90 codec */
383 #define BHND_PKGID_BCM4329_289PIN 0 /* 4329 289-pin package id */
384 #define BHND_PKGID_BCM4329_182PIN 1 /* 4329N 182-pin package id */
414 #define BHND_PKGID_BCM4314PCIE (8 | 2) /* 4314 QFN PCI (ARM-less) package id */
415 #define BHND_PKGID_BCM4314SDIO_ARM (8 | 3) /* 4314 QFN SDIO (ARM-less) package id */
438 #define BHND_COREID_V90_CODEC 0x807 /* v90 codec core */
468 #define BHND_COREID_ARM7S 0x825 /* ARM7tdmi-s core */
471 #define BHND_COREID_SSNPHY 0x828 /* 802.11n single-stream phy core */
488 #define BHND_COREID_APB_BRIDGE 0x135 /* BP135 AMBA AXI-APB bridge */
514 * PrimeCell-compatible BCM4331 cores, but due to lack of documentation, the
529 /** Evaluates to true if @p _type is a BCMA or BCMA-compatible interconenct */
548 #define BHND_BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
584 #define BHND_BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
595 #define BHND_BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
596 #define BHND_BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */
597 #define BHND_BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */
599 #define BHND_BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
602 #define BHND_BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */
609 #define BHND_BFL2_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are controlled by analog PA ctrl lines */
610 #define BHND_BFL2_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are controlled by analog PA ctrl lines */
611 #define BHND_BFL2_ELNACTRL_TRSW_2G 0x00400000 /* AZW4329: 2G gmode_elna_gain controls TR Switch */
630 /* SROM 11 - 11ac boardflag definitions */
636 #define BHND_BFL2_SROM11_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
637 #define BHND_BFL2_SROM11_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are ctrl-ed by analog PA ctrl lines …
638 #define BHND_BFL2_SROM11_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are ctrl-ed by analog PA ctrl lines …
663 #define BHND_BFL3_EN_NONBRCM_TXBF 0x10000000 /* acphy, enable non-brcm TXBF */
666 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
673 #define BHND_GPIO_BOARD_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
742 /* 11a-only minipci */