Lines Matching +full:tse +full:- +full:mdio
4 * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
116 #include "xgbe-common.h"
122 return (if_getmtu(pdata->netdev) + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in xgbe_get_max_frame()
131 rate = pdata->sysclk_rate; in xgbe_usec_to_riwt()
150 rate = pdata->sysclk_rate; in xgbe_riwt_to_usec()
170 pbl = pdata->pbl; in xgbe_config_pbl_val()
172 if (pdata->pbl > 32) { in xgbe_config_pbl_val()
177 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_pbl_val()
178 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, in xgbe_config_pbl_val()
181 if (pdata->channel[i]->tx_ring) in xgbe_config_pbl_val()
182 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, in xgbe_config_pbl_val()
185 if (pdata->channel[i]->rx_ring) in xgbe_config_pbl_val()
186 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, in xgbe_config_pbl_val()
198 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_osp_mode()
199 if (!pdata->channel[i]->tx_ring) in xgbe_config_osp_mode()
202 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, in xgbe_config_osp_mode()
203 pdata->tx_osp_mode); in xgbe_config_osp_mode()
214 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rsf_mode()
225 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tsf_mode()
236 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_threshold()
247 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tx_threshold()
258 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_coalesce()
259 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_coalesce()
262 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, in xgbe_config_rx_coalesce()
263 pdata->rx_riwt); in xgbe_config_rx_coalesce()
280 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_buffer_size()
281 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_buffer_size()
284 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, in xgbe_config_rx_buffer_size()
285 pdata->rx_buf_size); in xgbe_config_rx_buffer_size()
294 int tso_enabled = (if_getcapenable(pdata->netdev) & IFCAP_TSO); in xgbe_config_tso_mode()
296 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_tso_mode()
297 if (!pdata->channel[i]->tx_ring) in xgbe_config_tso_mode()
301 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, tso_enabled ? 1 : 0); in xgbe_config_tso_mode()
312 pdata->sph_enable, sph_enable_flag); in xgbe_config_sph_mode()
314 if (pdata->sph_enable && sph_enable_flag) in xgbe_config_sph_mode()
317 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_sph_mode()
318 if (!pdata->channel[i]->rx_ring) in xgbe_config_sph_mode()
320 if (pdata->sph_enable && sph_enable_flag) { in xgbe_config_sph_mode()
322 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); in xgbe_config_sph_mode()
325 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 0); in xgbe_config_sph_mode()
328 /* per-channel confirmation of SPH being disabled/enabled */ in xgbe_config_sph_mode()
329 int val = XGMAC_DMA_IOREAD_BITS(pdata->channel[i], DMA_CH_CR, SPH); in xgbe_config_sph_mode()
334 if (pdata->sph_enable && sph_enable_flag) in xgbe_config_sph_mode()
345 mtx_lock(&pdata->rss_mutex); in xgbe_write_rss_reg()
348 ret = -EBUSY; in xgbe_write_rss_reg()
360 while (wait--) { in xgbe_write_rss_reg()
367 ret = -EBUSY; in xgbe_write_rss_reg()
370 mtx_unlock(&pdata->rss_mutex); in xgbe_write_rss_reg()
378 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(uint32_t); in xgbe_write_rss_hash_key()
379 unsigned int *key = (unsigned int *)&pdata->rss_key; in xgbe_write_rss_hash_key()
382 while (key_regs--) { in xgbe_write_rss_hash_key()
398 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { in xgbe_write_rss_lookup_table()
400 pdata->rss_table[i]); in xgbe_write_rss_lookup_table()
411 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); in xgbe_set_rss_hash_key()
421 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) in xgbe_set_rss_lookup_table()
422 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); in xgbe_set_rss_lookup_table()
432 if (!pdata->hw_feat.rss) in xgbe_enable_rss()
433 return (-EOPNOTSUPP); in xgbe_enable_rss()
446 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); in xgbe_enable_rss()
459 if (!pdata->hw_feat.rss) in xgbe_disable_rss()
460 return (-EOPNOTSUPP); in xgbe_disable_rss()
474 if (!pdata->hw_feat.rss) in xgbe_config_rss()
478 if (pdata->enable_rss) in xgbe_config_rss()
495 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_tx_flow_control()
500 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); in xgbe_disable_tx_flow_control()
521 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_enable_tx_flow_control()
524 if (pdata->rx_rfd[i]) { in xgbe_enable_tx_flow_control()
526 /* TODO - enable pfc/ets support */ in xgbe_enable_tx_flow_control()
538 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); in xgbe_enable_tx_flow_control()
576 if (pdata->tx_pause) in xgbe_config_tx_flow_control()
587 if (pdata->rx_pause) in xgbe_config_rx_flow_control()
611 if (pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
613 pdata->channel_irq_mode); in xgbe_enable_dma_interrupts()
615 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); in xgbe_enable_dma_interrupts()
617 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_dma_interrupts()
618 channel = pdata->channel[i]; in xgbe_enable_dma_interrupts()
625 channel->curr_ier = 0; in xgbe_enable_dma_interrupts()
628 * NIE - Normal Interrupt Summary Enable in xgbe_enable_dma_interrupts()
629 * AIE - Abnormal Interrupt Summary Enable in xgbe_enable_dma_interrupts()
630 * FBEE - Fatal Bus Error Enable in xgbe_enable_dma_interrupts()
633 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1); in xgbe_enable_dma_interrupts()
634 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1); in xgbe_enable_dma_interrupts()
636 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1); in xgbe_enable_dma_interrupts()
637 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1); in xgbe_enable_dma_interrupts()
639 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); in xgbe_enable_dma_interrupts()
641 if (channel->tx_ring) { in xgbe_enable_dma_interrupts()
643 * TIE - Transmit Interrupt Enable (unless using in xgbe_enable_dma_interrupts()
647 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
648 XGMAC_SET_BITS(channel->curr_ier, in xgbe_enable_dma_interrupts()
651 if (channel->rx_ring) { in xgbe_enable_dma_interrupts()
653 * RBUE - Receive Buffer Unavailable Enable in xgbe_enable_dma_interrupts()
654 * RIE - Receive Interrupt Enable (unless using in xgbe_enable_dma_interrupts()
658 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); in xgbe_enable_dma_interrupts()
659 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
660 XGMAC_SET_BITS(channel->curr_ier, in xgbe_enable_dma_interrupts()
664 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); in xgbe_enable_dma_interrupts()
674 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); in xgbe_enable_mtl_interrupts()
699 /* Enable MDIO single command completion interrupt */ in xgbe_enable_mac_interrupts()
719 return (-EINVAL); in xgbe_set_speed()
737 /* Check only C-TAG (0x8100) packets */ in xgbe_enable_rx_vlan_stripping()
740 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ in xgbe_enable_rx_vlan_stripping()
773 /* Only filter on the lower 12-bits of the VLAN tag */ in xgbe_enable_rx_vlan_filtering()
837 bit_foreach(pdata->active_vlans, VLAN_NVID, vid) { in xgbe_update_vlan_hash_table()
874 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) { in xgbe_set_promiscuous_mode()
934 addn_macs = pdata->hw_feat.addn_mac; in xgbe_set_mac_addn_addrs()
936 xgbe_set_mac_reg(pdata, pdata->mac_addr, &mac_reg); in xgbe_set_mac_addn_addrs()
937 addn_macs--; in xgbe_set_mac_addn_addrs()
940 while (addn_macs--) in xgbe_set_mac_addn_addrs()
947 /* TODO - add support to set mac hash table */ in xgbe_add_mac_addresses()
973 pr_mode = ((if_getflags(pdata->netdev) & IFF_PROMISC) != 0); in xgbe_config_rx_mode()
974 am_mode = ((if_getflags(pdata->netdev) & IFF_ALLMULTI) != 0); in xgbe_config_rx_mode()
990 return (-EINVAL); in xgbe_clr_gpio()
1006 return (-EINVAL); in xgbe_set_gpio()
1026 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_read_mmd_regs_v2()
1033 * The mmio interface is based on 16-bit offsets and values. All in xgbe_read_mmd_regs_v2()
1038 index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_read_mmd_regs_v2()
1039 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_read_mmd_regs_v2()
1041 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1042 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_read_mmd_regs_v2()
1044 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1059 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_write_mmd_regs_v2()
1066 * The mmio interface is based on 16-bit offsets and values. All in xgbe_write_mmd_regs_v2()
1071 index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_write_mmd_regs_v2()
1072 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_write_mmd_regs_v2()
1074 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1075 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_write_mmd_regs_v2()
1077 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1090 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_read_mmd_regs_v1()
1097 * The mmio interface is based on 32-bit offsets and values. All in xgbe_read_mmd_regs_v1()
1101 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1104 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1119 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_write_mmd_regs_v1()
1126 * The mmio interface is based on 32-bit offsets and values. All in xgbe_write_mmd_regs_v1()
1130 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1133 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1139 switch (pdata->vdata->xpcs_access) { in xgbe_read_mmd_regs()
1153 switch (pdata->vdata->xpcs_access) { in xgbe_write_mmd_regs()
1184 mtx_lock_spin(&pdata->mdio_mutex); in xgbe_write_ext_mii_regs()
1195 if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) == in xgbe_write_ext_mii_regs()
1197 axgbe_error("%s: MDIO write error\n", __func__); in xgbe_write_ext_mii_regs()
1198 mtx_unlock_spin(&pdata->mdio_mutex); in xgbe_write_ext_mii_regs()
1199 return (-ETIMEDOUT); in xgbe_write_ext_mii_regs()
1202 mtx_unlock_spin(&pdata->mdio_mutex); in xgbe_write_ext_mii_regs()
1211 mtx_lock_spin(&pdata->mdio_mutex); in xgbe_read_ext_mii_regs()
1221 if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) == in xgbe_read_ext_mii_regs()
1223 axgbe_error("%s: MDIO read error\n", __func__); in xgbe_read_ext_mii_regs()
1224 mtx_unlock_spin(&pdata->mdio_mutex); in xgbe_read_ext_mii_regs()
1225 return (-ETIMEDOUT); in xgbe_read_ext_mii_regs()
1228 mtx_unlock_spin(&pdata->mdio_mutex); in xgbe_read_ext_mii_regs()
1242 return (-EINVAL); in xgbe_set_ext_mii_mode()
1248 return (-EINVAL); in xgbe_set_ext_mii_mode()
1259 return (!XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN)); in xgbe_tx_complete()
1283 struct xgbe_ring_desc *rdesc = rdata->rdesc; in xgbe_tx_desc_reset()
1291 rdesc->desc0 = 0; in xgbe_tx_desc_reset()
1292 rdesc->desc1 = 0; in xgbe_tx_desc_reset()
1293 rdesc->desc2 = 0; in xgbe_tx_desc_reset()
1294 rdesc->desc3 = 0; in xgbe_tx_desc_reset()
1302 struct xgbe_ring *ring = channel->tx_ring; in xgbe_tx_desc_init()
1305 int start_index = ring->cur; in xgbe_tx_desc_init()
1308 for (i = 0; i < ring->rdesc_count; i++) { in xgbe_tx_desc_init()
1316 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); in xgbe_tx_desc_init()
1321 upper_32_bits(rdata->rdata_paddr)); in xgbe_tx_desc_init()
1323 lower_32_bits(rdata->rdata_paddr)); in xgbe_tx_desc_init()
1329 struct xgbe_ring *ring = channel->rx_ring; in xgbe_rx_desc_init()
1331 unsigned int start_index = ring->cur; in xgbe_rx_desc_init()
1339 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); in xgbe_rx_desc_init()
1344 upper_32_bits(rdata->rdata_paddr)); in xgbe_rx_desc_init()
1346 lower_32_bits(rdata->rdata_paddr)); in xgbe_rx_desc_init()
1352 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_dev_read()
1353 struct xgbe_ring *ring = channel->rx_ring; in xgbe_dev_read()
1356 struct xgbe_packet_data *packet = &ring->packet_data; in xgbe_dev_read()
1359 axgbe_printf(1, "-->xgbe_dev_read: cur = %d\n", ring->cur); in xgbe_dev_read()
1361 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); in xgbe_dev_read()
1362 rdesc = rdata->rdesc; in xgbe_dev_read()
1365 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) in xgbe_dev_read()
1370 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { in xgbe_dev_read()
1371 /* TODO - Timestamp Context Descriptor */ in xgbe_dev_read()
1372 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1374 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1380 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); in xgbe_dev_read()
1383 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) in xgbe_dev_read()
1384 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1388 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { in xgbe_dev_read()
1389 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1391 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, in xgbe_dev_read()
1393 if (rdata->rx.hdr_len) in xgbe_dev_read()
1394 pdata->ext_stats.rx_split_header_packets++; in xgbe_dev_read()
1396 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1400 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { in xgbe_dev_read()
1401 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1404 packet->rss_hash = le32_to_cpu(rdesc->desc1); in xgbe_dev_read()
1406 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); in xgbe_dev_read()
1409 packet->rss_hash_type = M_HASHTYPE_RSS_TCP_IPV4; in xgbe_dev_read()
1412 packet->rss_hash_type = M_HASHTYPE_RSS_UDP_IPV4; in xgbe_dev_read()
1415 packet->rss_hash_type = M_HASHTYPE_RSS_TCP_IPV6; in xgbe_dev_read()
1418 packet->rss_hash_type = M_HASHTYPE_RSS_UDP_IPV6; in xgbe_dev_read()
1421 packet->rss_hash_type = M_HASHTYPE_OPAQUE; in xgbe_dev_read()
1427 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) { in xgbe_dev_read()
1429 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1435 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1439 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); in xgbe_dev_read()
1442 /* TODO - add tunneling support */ in xgbe_dev_read()
1443 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1447 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); in xgbe_dev_read()
1448 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); in xgbe_dev_read()
1454 (if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) { in xgbe_dev_read()
1455 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1457 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, in xgbe_dev_read()
1459 axgbe_printf(1, "vlan-ctag=%#06x\n", packet->vlan_ctag); in xgbe_dev_read()
1462 unsigned int tnp = XGMAC_GET_BITS(packet->attributes, in xgbe_dev_read()
1468 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1470 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1472 pdata->ext_stats.rx_csum_errors++; in xgbe_dev_read()
1476 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1478 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, in xgbe_dev_read()
1480 pdata->ext_stats.rx_vxlan_csum_errors++; in xgbe_dev_read()
1485 __func__, channel->queue_index, in xgbe_dev_read()
1489 __func__, ring->cur, ring->dirty); in xgbe_dev_read()
1490 axgbe_printf(1, "%s: Desc 0x%08x-0x%08x-0x%08x-0x%08x\n", in xgbe_dev_read()
1491 __func__, rdesc->desc0, rdesc->desc1, rdesc->desc2, in xgbe_dev_read()
1492 rdesc->desc3); in xgbe_dev_read()
1493 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, in xgbe_dev_read()
1498 axgbe_printf(1, "<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", in xgbe_dev_read()
1499 channel->name, ring->cur & (ring->rdesc_count - 1), ring->cur); in xgbe_dev_read()
1508 return (XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT)); in xgbe_is_context_desc()
1515 return (XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD)); in xgbe_is_last_desc()
1521 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_enable_int()
1523 axgbe_printf(1, "enable_int: DMA_CH_IER read - 0x%x\n", in xgbe_enable_int()
1524 channel->curr_ier); in xgbe_enable_int()
1528 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); in xgbe_enable_int()
1531 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1); in xgbe_enable_int()
1534 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1); in xgbe_enable_int()
1537 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); in xgbe_enable_int()
1540 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); in xgbe_enable_int()
1543 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1); in xgbe_enable_int()
1546 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); in xgbe_enable_int()
1547 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); in xgbe_enable_int()
1550 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); in xgbe_enable_int()
1553 channel->curr_ier |= channel->saved_ier; in xgbe_enable_int()
1556 return (-1); in xgbe_enable_int()
1559 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); in xgbe_enable_int()
1561 axgbe_printf(1, "enable_int: DMA_CH_IER write - 0x%x\n", in xgbe_enable_int()
1562 channel->curr_ier); in xgbe_enable_int()
1570 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_disable_int()
1572 axgbe_printf(1, "disable_int: DMA_CH_IER read - 0x%x\n", in xgbe_disable_int()
1573 channel->curr_ier); in xgbe_disable_int()
1577 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); in xgbe_disable_int()
1580 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0); in xgbe_disable_int()
1583 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0); in xgbe_disable_int()
1586 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); in xgbe_disable_int()
1589 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0); in xgbe_disable_int()
1592 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0); in xgbe_disable_int()
1595 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); in xgbe_disable_int()
1596 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); in xgbe_disable_int()
1599 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0); in xgbe_disable_int()
1602 channel->saved_ier = channel->curr_ier; in xgbe_disable_int()
1603 channel->curr_ier = 0; in xgbe_disable_int()
1606 return (-1); in xgbe_disable_int()
1609 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); in xgbe_disable_int()
1611 axgbe_printf(1, "disable_int: DMA_CH_IER write - 0x%x\n", in xgbe_disable_int()
1612 channel->curr_ier); in xgbe_disable_int()
1627 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) in __xgbe_exit()
1631 return (-EBUSY); in __xgbe_exit()
1658 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) in xgbe_flush_tx_queues()
1661 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_flush_tx_queues()
1665 for (i = 0; i < pdata->tx_q_count; i++) { in xgbe_flush_tx_queues()
1667 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, in xgbe_flush_tx_queues()
1672 return (-EBUSY); in xgbe_flush_tx_queues()
1690 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); in xgbe_config_dma_bus()
1691 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); in xgbe_config_dma_bus()
1692 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); in xgbe_config_dma_bus()
1693 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); in xgbe_config_dma_bus()
1698 if (pdata->vdata->tx_desc_prefetch) in xgbe_config_dma_bus()
1700 pdata->vdata->tx_desc_prefetch); in xgbe_config_dma_bus()
1702 if (pdata->vdata->rx_desc_prefetch) in xgbe_config_dma_bus()
1704 pdata->vdata->rx_desc_prefetch); in xgbe_config_dma_bus()
1710 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); in xgbe_config_dma_cache()
1711 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); in xgbe_config_dma_cache()
1712 if (pdata->awarcr) in xgbe_config_dma_cache()
1713 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); in xgbe_config_dma_cache()
1725 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_mtl_mode()
1746 /* TODO - add pfc/ets related support */ in xgbe_queue_flow_control_threshold()
1755 pdata->rx_rfa[queue] = 0; in xgbe_queue_flow_control_threshold()
1756 pdata->rx_rfd[queue] = 0; in xgbe_queue_flow_control_threshold()
1762 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ in xgbe_queue_flow_control_threshold()
1763 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ in xgbe_queue_flow_control_threshold()
1768 /* Between 4096 and max-frame */ in xgbe_queue_flow_control_threshold()
1769 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ in xgbe_queue_flow_control_threshold()
1770 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ in xgbe_queue_flow_control_threshold()
1775 /* Between max-frame and 3 max-frames, in xgbe_queue_flow_control_threshold()
1779 rfa = q_fifo_size - frame_fifo_size; in xgbe_queue_flow_control_threshold()
1782 /* Above 3 max-frames - trigger when just over in xgbe_queue_flow_control_threshold()
1790 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); in xgbe_queue_flow_control_threshold()
1791 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); in xgbe_queue_flow_control_threshold()
1793 queue, pdata->rx_rfa[queue], pdata->rx_rfd[queue]); in xgbe_queue_flow_control_threshold()
1803 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_calculate_flow_control_threshold()
1806 axgbe_printf(1, "%s: fifo[%d] - 0x%x q_fifo_size 0x%x\n", in xgbe_calculate_flow_control_threshold()
1817 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_config_flow_control_threshold()
1819 pdata->rx_rfa[i], pdata->rx_rfd[i]); in xgbe_config_flow_control_threshold()
1822 pdata->rx_rfa[i]); in xgbe_config_flow_control_threshold()
1824 pdata->rx_rfd[i]); in xgbe_config_flow_control_threshold()
1835 return (min_t(unsigned int, pdata->tx_max_fifo_size, in xgbe_get_tx_fifo_size()
1836 pdata->hw_feat.tx_fifo_size)); in xgbe_get_tx_fifo_size()
1843 return (min_t(unsigned int, pdata->rx_max_fifo_size, in xgbe_get_rx_fifo_size()
1844 pdata->hw_feat.rx_fifo_size)); in xgbe_get_rx_fifo_size()
1863 p_fifo--; in xgbe_calculate_equal_fifo()
1886 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1; in xgbe_set_nonprio_fifos()
1887 fifo_size -= XGMAC_FIFO_MIN_ALLOC; in xgbe_set_nonprio_fifos()
1903 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); in xgbe_config_tx_fifo_size()
1905 for (i = 0; i < pdata->tx_q_count; i++) { in xgbe_config_tx_fifo_size()
1912 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); in xgbe_config_tx_fifo_size()
1923 /* TODO - add pfc/ets related support */ in xgbe_config_rx_fifo_size()
1927 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_rx_fifo_size()
1929 fifo_size, pdata->rx_q_count, prio_queues); in xgbe_config_rx_fifo_size()
1931 /* Assign a minimum fifo to the non-VLAN priority queues */ in xgbe_config_rx_fifo_size()
1932 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); in xgbe_config_rx_fifo_size()
1936 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_config_rx_fifo_size()
1946 pdata->rx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); in xgbe_config_rx_fifo_size()
1961 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
1962 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
1964 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_queue_mapping()
1969 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
1976 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
1981 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_queue_mapping()
1992 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
1998 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2014 for (i = 0; i < pdata->rx_q_count;) { in xgbe_config_queue_mapping()
2017 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) in xgbe_config_queue_mapping()
2030 xgbe_set_mac_address(pdata, if_getlladdr(pdata->netdev)); in xgbe_config_mac_address()
2039 if (pdata->hw_feat.hash_table_size) { in xgbe_config_mac_address()
2051 val = (if_getmtu(pdata->netdev) > XGMAC_STD_PACKET_MTU) ? 1 : 0; in xgbe_config_jumbo_enable()
2059 xgbe_set_speed(pdata, pdata->phy_speed); in xgbe_config_mac_speed()
2065 if ((if_getcapenable(pdata->netdev) & IFCAP_RXCSUM)) in xgbe_config_checksum_offload()
2081 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) { in xgbe_config_vlan_support()
2089 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) { in xgbe_config_vlan_support()
2104 if (pdata->vdata->mmc_64bit) { in xgbe_mmc_read()
2144 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_tx_mmc_int()
2148 stats->txoctetcount_gb += in xgbe_tx_mmc_int()
2152 stats->txframecount_gb += in xgbe_tx_mmc_int()
2156 stats->txbroadcastframes_g += in xgbe_tx_mmc_int()
2160 stats->txmulticastframes_g += in xgbe_tx_mmc_int()
2164 stats->tx64octets_gb += in xgbe_tx_mmc_int()
2168 stats->tx65to127octets_gb += in xgbe_tx_mmc_int()
2172 stats->tx128to255octets_gb += in xgbe_tx_mmc_int()
2176 stats->tx256to511octets_gb += in xgbe_tx_mmc_int()
2180 stats->tx512to1023octets_gb += in xgbe_tx_mmc_int()
2184 stats->tx1024tomaxoctets_gb += in xgbe_tx_mmc_int()
2188 stats->txunicastframes_gb += in xgbe_tx_mmc_int()
2192 stats->txmulticastframes_gb += in xgbe_tx_mmc_int()
2196 stats->txbroadcastframes_g += in xgbe_tx_mmc_int()
2200 stats->txunderflowerror += in xgbe_tx_mmc_int()
2204 stats->txoctetcount_g += in xgbe_tx_mmc_int()
2208 stats->txframecount_g += in xgbe_tx_mmc_int()
2212 stats->txpauseframes += in xgbe_tx_mmc_int()
2216 stats->txvlanframes_g += in xgbe_tx_mmc_int()
2223 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_rx_mmc_int()
2227 stats->rxframecount_gb += in xgbe_rx_mmc_int()
2231 stats->rxoctetcount_gb += in xgbe_rx_mmc_int()
2235 stats->rxoctetcount_g += in xgbe_rx_mmc_int()
2239 stats->rxbroadcastframes_g += in xgbe_rx_mmc_int()
2243 stats->rxmulticastframes_g += in xgbe_rx_mmc_int()
2247 stats->rxcrcerror += in xgbe_rx_mmc_int()
2251 stats->rxrunterror += in xgbe_rx_mmc_int()
2255 stats->rxjabbererror += in xgbe_rx_mmc_int()
2259 stats->rxundersize_g += in xgbe_rx_mmc_int()
2263 stats->rxoversize_g += in xgbe_rx_mmc_int()
2267 stats->rx64octets_gb += in xgbe_rx_mmc_int()
2271 stats->rx65to127octets_gb += in xgbe_rx_mmc_int()
2275 stats->rx128to255octets_gb += in xgbe_rx_mmc_int()
2279 stats->rx256to511octets_gb += in xgbe_rx_mmc_int()
2283 stats->rx512to1023octets_gb += in xgbe_rx_mmc_int()
2287 stats->rx1024tomaxoctets_gb += in xgbe_rx_mmc_int()
2291 stats->rxunicastframes_g += in xgbe_rx_mmc_int()
2295 stats->rxlengtherror += in xgbe_rx_mmc_int()
2299 stats->rxoutofrangetype += in xgbe_rx_mmc_int()
2303 stats->rxpauseframes += in xgbe_rx_mmc_int()
2307 stats->rxfifooverflow += in xgbe_rx_mmc_int()
2311 stats->rxvlanframes_gb += in xgbe_rx_mmc_int()
2315 stats->rxwatchdogerror += in xgbe_rx_mmc_int()
2322 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_read_mmc_stats()
2327 stats->txoctetcount_gb += in xgbe_read_mmc_stats()
2330 stats->txframecount_gb += in xgbe_read_mmc_stats()
2333 stats->txbroadcastframes_g += in xgbe_read_mmc_stats()
2336 stats->txmulticastframes_g += in xgbe_read_mmc_stats()
2339 stats->tx64octets_gb += in xgbe_read_mmc_stats()
2342 stats->tx65to127octets_gb += in xgbe_read_mmc_stats()
2345 stats->tx128to255octets_gb += in xgbe_read_mmc_stats()
2348 stats->tx256to511octets_gb += in xgbe_read_mmc_stats()
2351 stats->tx512to1023octets_gb += in xgbe_read_mmc_stats()
2354 stats->tx1024tomaxoctets_gb += in xgbe_read_mmc_stats()
2357 stats->txunicastframes_gb += in xgbe_read_mmc_stats()
2360 stats->txmulticastframes_gb += in xgbe_read_mmc_stats()
2363 stats->txbroadcastframes_gb += in xgbe_read_mmc_stats()
2366 stats->txunderflowerror += in xgbe_read_mmc_stats()
2369 stats->txoctetcount_g += in xgbe_read_mmc_stats()
2372 stats->txframecount_g += in xgbe_read_mmc_stats()
2375 stats->txpauseframes += in xgbe_read_mmc_stats()
2378 stats->txvlanframes_g += in xgbe_read_mmc_stats()
2381 stats->rxframecount_gb += in xgbe_read_mmc_stats()
2384 stats->rxoctetcount_gb += in xgbe_read_mmc_stats()
2387 stats->rxoctetcount_g += in xgbe_read_mmc_stats()
2390 stats->rxbroadcastframes_g += in xgbe_read_mmc_stats()
2393 stats->rxmulticastframes_g += in xgbe_read_mmc_stats()
2396 stats->rxcrcerror += in xgbe_read_mmc_stats()
2399 stats->rxrunterror += in xgbe_read_mmc_stats()
2402 stats->rxjabbererror += in xgbe_read_mmc_stats()
2405 stats->rxundersize_g += in xgbe_read_mmc_stats()
2408 stats->rxoversize_g += in xgbe_read_mmc_stats()
2411 stats->rx64octets_gb += in xgbe_read_mmc_stats()
2414 stats->rx65to127octets_gb += in xgbe_read_mmc_stats()
2417 stats->rx128to255octets_gb += in xgbe_read_mmc_stats()
2420 stats->rx256to511octets_gb += in xgbe_read_mmc_stats()
2423 stats->rx512to1023octets_gb += in xgbe_read_mmc_stats()
2426 stats->rx1024tomaxoctets_gb += in xgbe_read_mmc_stats()
2429 stats->rxunicastframes_g += in xgbe_read_mmc_stats()
2432 stats->rxlengtherror += in xgbe_read_mmc_stats()
2435 stats->rxoutofrangetype += in xgbe_read_mmc_stats()
2438 stats->rxpauseframes += in xgbe_read_mmc_stats()
2441 stats->rxfifooverflow += in xgbe_read_mmc_stats()
2444 stats->rxvlanframes_gb += in xgbe_read_mmc_stats()
2447 stats->rxwatchdogerror += in xgbe_read_mmc_stats()
2450 /* Un-freeze counters */ in xgbe_read_mmc_stats()
2496 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) in xgbe_prepare_tx_stop()
2504 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE; in xgbe_prepare_tx_stop()
2537 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_tx()
2538 if (!pdata->channel[i]->tx_ring) in xgbe_enable_tx()
2541 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_enable_tx()
2545 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_enable_tx()
2559 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
2566 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
2570 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_tx()
2571 if (!pdata->channel[i]->tx_ring) in xgbe_disable_tx()
2574 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_disable_tx()
2609 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_rx()
2610 if (!pdata->channel[i]->rx_ring) in xgbe_enable_rx()
2613 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_enable_rx()
2618 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_enable_rx()
2641 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_rx()
2648 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_rx()
2649 if (!pdata->channel[i]->rx_ring) in xgbe_disable_rx()
2652 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_disable_rx()
2662 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_tx()
2663 if (!pdata->channel[i]->tx_ring) in xgbe_powerup_tx()
2666 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_powerup_tx()
2679 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_powerdown_tx()
2686 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_tx()
2687 if (!pdata->channel[i]->tx_ring) in xgbe_powerdown_tx()
2690 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_powerdown_tx()
2700 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_rx()
2701 if (!pdata->channel[i]->rx_ring) in xgbe_powerup_rx()
2704 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_powerup_rx()
2714 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_rx()
2715 if (!pdata->channel[i]->rx_ring) in xgbe_powerdown_rx()
2718 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_powerdown_rx()
2725 struct xgbe_desc_if *desc_if = &pdata->desc_if; in xgbe_init()
2748 desc_if->wrapper_tx_desc_init(pdata); in xgbe_init()
2749 desc_if->wrapper_rx_desc_init(pdata); in xgbe_init()
2757 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); in xgbe_init()
2758 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); in xgbe_init()
2759 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); in xgbe_init()
2760 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); in xgbe_init()
2788 hw_if->tx_complete = xgbe_tx_complete; in xgbe_init_function_ptrs_dev()
2790 hw_if->set_mac_address = xgbe_set_mac_address; in xgbe_init_function_ptrs_dev()
2791 hw_if->config_rx_mode = xgbe_config_rx_mode; in xgbe_init_function_ptrs_dev()
2793 hw_if->enable_rx_csum = xgbe_enable_rx_csum; in xgbe_init_function_ptrs_dev()
2794 hw_if->disable_rx_csum = xgbe_disable_rx_csum; in xgbe_init_function_ptrs_dev()
2796 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; in xgbe_init_function_ptrs_dev()
2797 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; in xgbe_init_function_ptrs_dev()
2798 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; in xgbe_init_function_ptrs_dev()
2799 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; in xgbe_init_function_ptrs_dev()
2800 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; in xgbe_init_function_ptrs_dev()
2802 hw_if->read_mmd_regs = xgbe_read_mmd_regs; in xgbe_init_function_ptrs_dev()
2803 hw_if->write_mmd_regs = xgbe_write_mmd_regs; in xgbe_init_function_ptrs_dev()
2805 hw_if->set_speed = xgbe_set_speed; in xgbe_init_function_ptrs_dev()
2807 hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode; in xgbe_init_function_ptrs_dev()
2808 hw_if->read_ext_mii_regs = xgbe_read_ext_mii_regs; in xgbe_init_function_ptrs_dev()
2809 hw_if->write_ext_mii_regs = xgbe_write_ext_mii_regs; in xgbe_init_function_ptrs_dev()
2811 hw_if->set_gpio = xgbe_set_gpio; in xgbe_init_function_ptrs_dev()
2812 hw_if->clr_gpio = xgbe_clr_gpio; in xgbe_init_function_ptrs_dev()
2814 hw_if->enable_tx = xgbe_enable_tx; in xgbe_init_function_ptrs_dev()
2815 hw_if->disable_tx = xgbe_disable_tx; in xgbe_init_function_ptrs_dev()
2816 hw_if->enable_rx = xgbe_enable_rx; in xgbe_init_function_ptrs_dev()
2817 hw_if->disable_rx = xgbe_disable_rx; in xgbe_init_function_ptrs_dev()
2819 hw_if->powerup_tx = xgbe_powerup_tx; in xgbe_init_function_ptrs_dev()
2820 hw_if->powerdown_tx = xgbe_powerdown_tx; in xgbe_init_function_ptrs_dev()
2821 hw_if->powerup_rx = xgbe_powerup_rx; in xgbe_init_function_ptrs_dev()
2822 hw_if->powerdown_rx = xgbe_powerdown_rx; in xgbe_init_function_ptrs_dev()
2824 hw_if->dev_read = xgbe_dev_read; in xgbe_init_function_ptrs_dev()
2825 hw_if->enable_int = xgbe_enable_int; in xgbe_init_function_ptrs_dev()
2826 hw_if->disable_int = xgbe_disable_int; in xgbe_init_function_ptrs_dev()
2827 hw_if->init = xgbe_init; in xgbe_init_function_ptrs_dev()
2828 hw_if->exit = xgbe_exit; in xgbe_init_function_ptrs_dev()
2831 hw_if->tx_desc_init = xgbe_tx_desc_init; in xgbe_init_function_ptrs_dev()
2832 hw_if->rx_desc_init = xgbe_rx_desc_init; in xgbe_init_function_ptrs_dev()
2833 hw_if->tx_desc_reset = xgbe_tx_desc_reset; in xgbe_init_function_ptrs_dev()
2834 hw_if->is_last_desc = xgbe_is_last_desc; in xgbe_init_function_ptrs_dev()
2835 hw_if->is_context_desc = xgbe_is_context_desc; in xgbe_init_function_ptrs_dev()
2838 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; in xgbe_init_function_ptrs_dev()
2839 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; in xgbe_init_function_ptrs_dev()
2842 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; in xgbe_init_function_ptrs_dev()
2843 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; in xgbe_init_function_ptrs_dev()
2844 hw_if->usec_to_riwt = xgbe_usec_to_riwt; in xgbe_init_function_ptrs_dev()
2845 hw_if->riwt_to_usec = xgbe_riwt_to_usec; in xgbe_init_function_ptrs_dev()
2848 hw_if->config_rx_threshold = xgbe_config_rx_threshold; in xgbe_init_function_ptrs_dev()
2849 hw_if->config_tx_threshold = xgbe_config_tx_threshold; in xgbe_init_function_ptrs_dev()
2852 hw_if->config_rsf_mode = xgbe_config_rsf_mode; in xgbe_init_function_ptrs_dev()
2853 hw_if->config_tsf_mode = xgbe_config_tsf_mode; in xgbe_init_function_ptrs_dev()
2856 hw_if->config_osp_mode = xgbe_config_osp_mode; in xgbe_init_function_ptrs_dev()
2859 hw_if->tx_mmc_int = xgbe_tx_mmc_int; in xgbe_init_function_ptrs_dev()
2860 hw_if->rx_mmc_int = xgbe_rx_mmc_int; in xgbe_init_function_ptrs_dev()
2861 hw_if->read_mmc_stats = xgbe_read_mmc_stats; in xgbe_init_function_ptrs_dev()
2864 hw_if->enable_rss = xgbe_enable_rss; in xgbe_init_function_ptrs_dev()
2865 hw_if->disable_rss = xgbe_disable_rss; in xgbe_init_function_ptrs_dev()
2866 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; in xgbe_init_function_ptrs_dev()
2867 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; in xgbe_init_function_ptrs_dev()