Lines Matching +full:0 +full:x0810
121 #define DMA_MR 0x3000
122 #define DMA_SBMR 0x3004
123 #define DMA_ISR 0x3008
124 #define DMA_AXIARCR 0x3010
125 #define DMA_AXIAWCR 0x3018
126 #define DMA_AXIAWARCR 0x301c
127 #define DMA_DSR0 0x3020
128 #define DMA_DSR1 0x3024
129 #define DMA_DSR2 0x3028
130 #define DMA_DSR3 0x302C
131 #define DMA_DSR4 0x3030
132 #define DMA_TXEDMACR 0x3040
133 #define DMA_RXEDMACR 0x3044
142 #define DMA_MR_SWR_INDEX 0
144 #define DMA_RXEDMACR_RDPS_INDEX 0
154 #define DMA_SBMR_UNDEF_INDEX 0
158 #define DMA_TXEDMACR_TDPS_INDEX 0
177 #define DMA_DSRX_RPS_START 0
179 #define DMA_TPS_STOPPED 0x00
180 #define DMA_TPS_SUSPENDED 0x06
184 * that begin at 0x3100. Each subsequent channel has registers that
185 * are accessed using an offset of 0x80 from the previous channel.
187 #define DMA_CH_BASE 0x3100
188 #define DMA_CH_INC 0x80
190 #define DMA_CH_CR 0x00
191 #define DMA_CH_TCR 0x04
192 #define DMA_CH_RCR 0x08
193 #define DMA_CH_TDLR_HI 0x10
194 #define DMA_CH_TDLR_LO 0x14
195 #define DMA_CH_RDLR_HI 0x18
196 #define DMA_CH_RDLR_LO 0x1c
197 #define DMA_CH_TDTR_LO 0x24
198 #define DMA_CH_RDTR_LO 0x2c
199 #define DMA_CH_TDRLR 0x30
200 #define DMA_CH_RDRLR 0x34
201 #define DMA_CH_IER 0x38
202 #define DMA_CH_RIWT 0x3c
203 #define DMA_CH_CATDR_LO 0x44
204 #define DMA_CH_CARDR_LO 0x4c
205 #define DMA_CH_CATBR_HI 0x50
206 #define DMA_CH_CATBR_LO 0x54
207 #define DMA_CH_CARBR_HI 0x58
208 #define DMA_CH_CARBR_LO 0x5c
209 #define DMA_CH_SR 0x60
210 #define DMA_CH_DSR 0x64
211 #define DMA_CH_DCFL 0x68
212 #define DMA_CH_MFC 0x6c
213 #define DMA_CH_TDTRO 0x70
214 #define DMA_CH_RDTRO 0x74
215 #define DMA_CH_TDWRO 0x78
216 #define DMA_CH_RDWRO 0x7C
241 #define DMA_CH_IER_TIE_INDEX 0
249 #define DMA_CH_RCR_SR_INDEX 0
251 #define DMA_CH_RIWT_RWT_INDEX 0
263 #define DMA_CH_SR_TI_INDEX 0
271 #define DMA_CH_TCR_ST_INDEX 0
277 #define DMA_OSP_DISABLE 0x00
278 #define DMA_OSP_ENABLE 0x01
288 #define DMA_PBL_X8_DISABLE 0x00
289 #define DMA_PBL_X8_ENABLE 0x01
292 #define MAC_TCR 0x0000
293 #define MAC_RCR 0x0004
294 #define MAC_PFR 0x0008
295 #define MAC_WTR 0x000c
296 #define MAC_HTR0 0x0010
297 #define MAC_HTR1 0x0014
298 #define MAC_HTR2 0x0018
299 #define MAC_HTR3 0x001c
300 #define MAC_HTR4 0x0020
301 #define MAC_HTR5 0x0024
302 #define MAC_HTR6 0x0028
303 #define MAC_HTR7 0x002c
304 #define MAC_VLANTR 0x0050
305 #define MAC_VLANHTR 0x0058
306 #define MAC_VLANIR 0x0060
307 #define MAC_IVLANIR 0x0064
308 #define MAC_RETMR 0x006c
309 #define MAC_Q0TFCR 0x0070
310 #define MAC_Q1TFCR 0x0074
311 #define MAC_Q2TFCR 0x0078
312 #define MAC_Q3TFCR 0x007c
313 #define MAC_Q4TFCR 0x0080
314 #define MAC_Q5TFCR 0x0084
315 #define MAC_Q6TFCR 0x0088
316 #define MAC_Q7TFCR 0x008c
317 #define MAC_RFCR 0x0090
318 #define MAC_RQC0R 0x00a0
319 #define MAC_RQC1R 0x00a4
320 #define MAC_RQC2R 0x00a8
321 #define MAC_RQC3R 0x00ac
322 #define MAC_ISR 0x00b0
323 #define MAC_IER 0x00b4
324 #define MAC_RTSR 0x00b8
325 #define MAC_PMTCSR 0x00c0
326 #define MAC_RWKPFR 0x00c4
327 #define MAC_LPICSR 0x00d0
328 #define MAC_LPITCR 0x00d4
329 #define MAC_TIR 0x00e0
330 #define MAC_VR 0x0110
331 #define MAC_DR 0x0114
332 #define MAC_HWF0R 0x011c
333 #define MAC_HWF1R 0x0120
334 #define MAC_HWF2R 0x0124
335 #define MAC_MDIOSCAR 0x0200
336 #define MAC_MDIOSCCDR 0x0204
337 #define MAC_MDIOISR 0x0214
338 #define MAC_MDIOIER 0x0218
339 #define MAC_MDIOCL22R 0x0220
340 #define MAC_GPIOCR 0x0278
341 #define MAC_GPIOSR 0x027c
342 #define MAC_MACA0HR 0x0300
343 #define MAC_MACA0LR 0x0304
344 #define MAC_MACA1HR 0x0308
345 #define MAC_MACA1LR 0x030c
346 #define MAC_RSSCR 0x0c80
347 #define MAC_RSSAR 0x0c88
348 #define MAC_RSSDR 0x0c8c
349 #define MAC_TSCR 0x0d00
350 #define MAC_SSIR 0x0d04
351 #define MAC_STSR 0x0d08
352 #define MAC_STNR 0x0d0c
353 #define MAC_STSUR 0x0d10
354 #define MAC_STNUR 0x0d14
355 #define MAC_TSAR 0x0d18
356 #define MAC_TSSR 0x0d20
357 #define MAC_TXSNR 0x0d30
358 #define MAC_TXSSR 0x0d34
414 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0
428 #define MAC_HWF2R_RXQCNT_INDEX 0
456 #define MAC_MDIOSCAR_RA_INDEX 0
464 #define MAC_MDIOSCCDR_DATA_INDEX 0
476 #define MAC_PFR_PR_INDEX 0
486 #define MAC_PMTCSR_PWRDWN_INDEX 0
510 #define MAC_RCR_RE_INDEX 0
516 #define MAC_RFCR_RFE_INDEX 0
520 #define MAC_RQC0R_RXQ0EN_INDEX 0
526 #define MAC_RSSAR_OB_INDEX 0
532 #define MAC_RSSCR_RSSE_INDEX 0
538 #define MAC_RSSDR_DMCH_INDEX 0
546 #define MAC_TCR_TE_INDEX 0
552 #define MAC_TIR_TNID_INDEX 0
564 #define MAC_TSCR_TSENA_INDEX 0
588 #define MAC_VLANHTR_VLHT_INDEX 0
606 #define MAC_VLANTR_VL_INDEX 0
614 #define MAC_VR_SNPSVER_INDEX 0
620 #define MMC_CR 0x0800
621 #define MMC_RISR 0x0804
622 #define MMC_TISR 0x0808
623 #define MMC_RIER 0x080c
624 #define MMC_TIER 0x0810
625 #define MMC_TXOCTETCOUNT_GB_LO 0x0814
626 #define MMC_TXOCTETCOUNT_GB_HI 0x0818
627 #define MMC_TXFRAMECOUNT_GB_LO 0x081c
628 #define MMC_TXFRAMECOUNT_GB_HI 0x0820
629 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824
630 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828
631 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c
632 #define MMC_TXMULTICASTFRAMES_G_HI 0x0830
633 #define MMC_TX64OCTETS_GB_LO 0x0834
634 #define MMC_TX64OCTETS_GB_HI 0x0838
635 #define MMC_TX65TO127OCTETS_GB_LO 0x083c
636 #define MMC_TX65TO127OCTETS_GB_HI 0x0840
637 #define MMC_TX128TO255OCTETS_GB_LO 0x0844
638 #define MMC_TX128TO255OCTETS_GB_HI 0x0848
639 #define MMC_TX256TO511OCTETS_GB_LO 0x084c
640 #define MMC_TX256TO511OCTETS_GB_HI 0x0850
641 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854
642 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858
643 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c
644 #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860
645 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864
646 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868
647 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c
648 #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870
649 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874
650 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878
651 #define MMC_TXUNDERFLOWERROR_LO 0x087c
652 #define MMC_TXUNDERFLOWERROR_HI 0x0880
653 #define MMC_TXOCTETCOUNT_G_LO 0x0884
654 #define MMC_TXOCTETCOUNT_G_HI 0x0888
655 #define MMC_TXFRAMECOUNT_G_LO 0x088c
656 #define MMC_TXFRAMECOUNT_G_HI 0x0890
657 #define MMC_TXPAUSEFRAMES_LO 0x0894
658 #define MMC_TXPAUSEFRAMES_HI 0x0898
659 #define MMC_TXVLANFRAMES_G_LO 0x089c
660 #define MMC_TXVLANFRAMES_G_HI 0x08a0
661 #define MMC_RXFRAMECOUNT_GB_LO 0x0900
662 #define MMC_RXFRAMECOUNT_GB_HI 0x0904
663 #define MMC_RXOCTETCOUNT_GB_LO 0x0908
664 #define MMC_RXOCTETCOUNT_GB_HI 0x090c
665 #define MMC_RXOCTETCOUNT_G_LO 0x0910
666 #define MMC_RXOCTETCOUNT_G_HI 0x0914
667 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918
668 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c
669 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920
670 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924
671 #define MMC_RXCRCERROR_LO 0x0928
672 #define MMC_RXCRCERROR_HI 0x092c
673 #define MMC_RXRUNTERROR 0x0930
674 #define MMC_RXJABBERERROR 0x0934
675 #define MMC_RXUNDERSIZE_G 0x0938
676 #define MMC_RXOVERSIZE_G 0x093c
677 #define MMC_RX64OCTETS_GB_LO 0x0940
678 #define MMC_RX64OCTETS_GB_HI 0x0944
679 #define MMC_RX65TO127OCTETS_GB_LO 0x0948
680 #define MMC_RX65TO127OCTETS_GB_HI 0x094c
681 #define MMC_RX128TO255OCTETS_GB_LO 0x0950
682 #define MMC_RX128TO255OCTETS_GB_HI 0x0954
683 #define MMC_RX256TO511OCTETS_GB_LO 0x0958
684 #define MMC_RX256TO511OCTETS_GB_HI 0x095c
685 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960
686 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964
687 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968
688 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c
689 #define MMC_RXUNICASTFRAMES_G_LO 0x0970
690 #define MMC_RXUNICASTFRAMES_G_HI 0x0974
691 #define MMC_RXLENGTHERROR_LO 0x0978
692 #define MMC_RXLENGTHERROR_HI 0x097c
693 #define MMC_RXOUTOFRANGETYPE_LO 0x0980
694 #define MMC_RXOUTOFRANGETYPE_HI 0x0984
695 #define MMC_RXPAUSEFRAMES_LO 0x0988
696 #define MMC_RXPAUSEFRAMES_HI 0x098c
697 #define MMC_RXFIFOOVERFLOW_LO 0x0990
698 #define MMC_RXFIFOOVERFLOW_HI 0x0994
699 #define MMC_RXVLANFRAMES_GB_LO 0x0998
700 #define MMC_RXVLANFRAMES_GB_HI 0x099c
701 #define MMC_RXWATCHDOGERROR 0x09a0
704 #define MMC_CR_CR_INDEX 0
714 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0
716 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0
762 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0
764 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0
802 #define MTL_OMR 0x1000
803 #define MTL_FDCR 0x1008
804 #define MTL_FDSR 0x100c
805 #define MTL_FDDR 0x1010
806 #define MTL_ISR 0x1020
807 #define MTL_RQDCM0R 0x1030
808 #define MTL_RQDCM1R 0x1034
809 #define MTL_RQDCM2R 0x1038
810 #define MTL_TCPM0R 0x1040
811 #define MTL_TCPM1R 0x1044
826 * that begin at 0x1100. Each subsequent queue has registers that
827 * are accessed using an offset of 0x80 from the previous queue.
829 #define MTL_Q_BASE 0x1100
830 #define MTL_Q_INC 0x80
832 #define MTL_Q_TQOMR 0x00
833 #define MTL_Q_TQUR 0x04
834 #define MTL_Q_TQDR 0x08
835 #define MTL_Q_TC0ETSCR 0x10
836 #define MTL_Q_TC0ETSSR 0x14
837 #define MTL_Q_TC0QWR 0x18
838 #define MTL_Q_RQOMR 0x40
839 #define MTL_Q_RQMPOCR 0x44
840 #define MTL_Q_RQDR 0x48
841 #define MTL_Q_RQCR 0x4c
842 #define MTL_Q_RQFCR 0x50
843 #define MTL_Q_IER 0x70
844 #define MTL_Q_ISR 0x74
861 #define MTL_Q_RQOMR_RTC_INDEX 0
867 #define MTL_Q_TQOMR_FTQ_INDEX 0
881 #define MTL_RSF_DISABLE 0x00
882 #define MTL_RSF_ENABLE 0x01
883 #define MTL_TSF_DISABLE 0x00
884 #define MTL_TSF_ENABLE 0x01
886 #define MTL_RX_THRESHOLD_64 0x00
887 #define MTL_RX_THRESHOLD_96 0x02
888 #define MTL_RX_THRESHOLD_128 0x03
889 #define MTL_TX_THRESHOLD_32 0x01
890 #define MTL_TX_THRESHOLD_64 0x00
891 #define MTL_TX_THRESHOLD_96 0x02
892 #define MTL_TX_THRESHOLD_128 0x03
893 #define MTL_TX_THRESHOLD_192 0x04
894 #define MTL_TX_THRESHOLD_256 0x05
895 #define MTL_TX_THRESHOLD_384 0x06
896 #define MTL_TX_THRESHOLD_512 0x07
898 #define MTL_ETSALG_WRR 0x00
899 #define MTL_ETSALG_WFQ 0x01
900 #define MTL_ETSALG_DWRR 0x02
901 #define MTL_RAA_SP 0x00
902 #define MTL_RAA_WSP 0x01
904 #define MTL_Q_DISABLED 0x00
905 #define MTL_Q_ENABLED 0x02
909 * that begin at 0x1100. Each subsequent queue has registers that
910 * are accessed using an offset of 0x80 from the previous queue.
915 #define MTL_TC_ETSCR 0x10
916 #define MTL_TC_ETSSR 0x14
917 #define MTL_TC_QWR 0x18
920 #define MTL_TC_ETSCR_TSA_INDEX 0
922 #define MTL_TC_QWR_QW_INDEX 0
926 #define MTL_TSA_SP 0x00
927 #define MTL_TSA_ETS 0x02
936 #define PCS_V1_WINDOW_SELECT 0x03fc
937 #define PCS_V2_WINDOW_DEF 0x9060
938 #define PCS_V2_WINDOW_SELECT 0x9064
939 #define PCS_V2_RV_WINDOW_DEF 0x1060
940 #define PCS_V2_RV_WINDOW_SELECT 0x1064
949 #define SIR0_KR_RT_1 0x002c
950 #define SIR0_STATUS 0x0040
951 #define SIR1_SPEED 0x0000
956 #define SIR0_STATUS_RX_READY_INDEX 0
970 #define SIR1_SPEED_WORDMODE_INDEX 0
974 #define RXTX_REG6 0x0018
975 #define RXTX_REG20 0x0050
976 #define RXTX_REG22 0x0058
977 #define RXTX_REG114 0x01c8
978 #define RXTX_REG129 0x0204
991 #define XP_PROP_0 0x0000
992 #define XP_PROP_1 0x0004
993 #define XP_PROP_2 0x0008
994 #define XP_PROP_3 0x000c
995 #define XP_PROP_4 0x0010
996 #define XP_PROP_5 0x0014
997 #define XP_MAC_ADDR_LO 0x0020
998 #define XP_MAC_ADDR_HI 0x0024
999 #define XP_ECC_ISR 0x0030
1000 #define XP_ECC_IER 0x0034
1001 #define XP_ECC_CNT0 0x003c
1002 #define XP_ECC_CNT1 0x0040
1003 #define XP_DRIVER_INT_REQ 0x0060
1004 #define XP_DRIVER_INT_RO 0x0064
1005 #define XP_DRIVER_SCRATCH_0 0x0068
1006 #define XP_DRIVER_SCRATCH_1 0x006c
1007 #define XP_INT_REISSUE_EN 0x0074
1008 #define XP_INT_EN 0x0078
1009 #define XP_I2C_MUTEX 0x0080
1010 #define XP_MDIO_MUTEX 0x0084
1013 #define XP_DRIVER_INT_REQ_REQUEST_INDEX 0
1015 #define XP_DRIVER_INT_RO_STATUS_INDEX 0
1017 #define XP_DRIVER_SCRATCH_0_COMMAND_INDEX 0
1027 #define XP_ECC_CNT0_TX_SEC_INDEX 0
1031 #define XP_ECC_CNT1_DESC_SEC_INDEX 0
1043 #define XP_ECC_IER_TX_SEC_INDEX 0
1055 #define XP_ECC_ISR_TX_SEC_INDEX 0
1061 #define XP_I2C_MUTEX_ACTIVE_INDEX 0
1069 #define XP_PROP_0_PORT_ID_INDEX 0
1081 #define XP_PROP_1_MAX_TX_QUEUES_INDEX 0
1085 #define XP_PROP_2_TX_FIFO_SIZE_INDEX 0
1099 #define XP_PROP_3_MDIO_RESET_INDEX 0
1109 #define XP_PROP_4_MUX_ADDR_LO_INDEX 0
1125 #define IC_CON 0x0000
1126 #define IC_TAR 0x0004
1127 #define IC_DATA_CMD 0x0010
1128 #define IC_INTR_STAT 0x002c
1129 #define IC_INTR_MASK 0x0030
1130 #define IC_RAW_INTR_STAT 0x0034
1131 #define IC_CLR_INTR 0x0040
1132 #define IC_CLR_TX_ABRT 0x0054
1133 #define IC_CLR_STOP_DET 0x0060
1134 #define IC_ENABLE 0x006c
1135 #define IC_TXFLR 0x0074
1136 #define IC_RXFLR 0x0078
1137 #define IC_TX_ABRT_SOURCE 0x0080
1138 #define IC_ENABLE_STATUS 0x009c
1139 #define IC_COMP_PARAM_1 0x00f4
1148 #define IC_CON_MASTER_MODE_INDEX 0
1164 #define IC_ENABLE_EN_INDEX 0
1166 #define IC_ENABLE_STATUS_EN_INDEX 0
1180 #define IC_TX_ABRT_7B_ADDR_NOACK 0x0001
1181 #define IC_TX_ABRT_ARB_LOST 0x1000
1188 #define RX_PACKET_ERRORS_LENGTH_INDEX 0
1193 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0
1214 #define RX_NORMAL_DESC0_OVT_INDEX 0
1216 #define RX_NORMAL_DESC2_HL_INDEX 0
1240 #define RX_NORMAL_DESC3_PL_INDEX 0
1259 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0
1270 #define TX_CONTEXT_DESC2_MSS_INDEX 0
1278 #define TX_CONTEXT_DESC3_VT_INDEX 0
1281 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0
1297 #define TX_NORMAL_DESC3_FL_INDEX 0
1305 #define TX_NORMAL_DESC3_TCPPL_INDEX 0
1312 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2
1313 #define TX_NORMAL_DESC3_VXLAN_PACKET 0x3
1317 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096
1321 #define MDIO_PMA_10GBR_FECCTRL 0x00ab
1325 #define MDIO_PMA_RX_CTRL1 0x8051
1329 #define MDIO_PCS_DIG_CTRL 0x8000
1333 #define MDIO_PCS_DIGITAL_STAT 0x8010
1337 #define MDIO_AN_XNP 0x0016
1341 #define MDIO_AN_LPX 0x0019
1345 #define MDIO_AN_COMP_STAT 0x0030
1349 #define MDIO_AN_INTMASK 0x8001
1353 #define MDIO_AN_INT 0x8002
1357 #define MDIO_VEND2_AN_ADVERTISE 0x0004
1361 #define MDIO_VEND2_AN_LP_ABILITY 0x0005
1365 #define MDIO_VEND2_AN_CTRL 0x8001
1369 #define MDIO_VEND2_AN_STAT 0x8002
1373 #define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
1377 #define MDIO_VEND2_PMA_MISC_CTRL0 0x8090
1401 #define XGBE_AN_CL73_INT_CMPLT BIT(0)
1404 #define XGBE_AN_CL73_INT_MASK 0x07
1406 #define XGBE_XNP_MCF_NULL_MESSAGE 0x001
1411 #define XGBE_KR_TRAINING_START BIT(0)
1415 #define XGBE_PCS_PSEQ_STATE_MASK 0x1c
1416 #define XGBE_PCS_PSEQ_STATE_POWER_GOOD 0x10
1418 #define XGBE_AN_CL37_INT_CMPLT BIT(0)
1419 #define XGBE_AN_CL37_INT_MASK 0x01
1421 #define XGBE_AN_CL37_HD_MASK 0x40
1422 #define XGBE_AN_CL37_FD_MASK 0x20
1424 #define XGBE_AN_CL37_PCS_MODE_MASK 0x06
1425 #define XGBE_AN_CL37_PCS_MODE_BASEX 0x00
1426 #define XGBE_AN_CL37_PCS_MODE_SGMII 0x04
1427 #define XGBE_AN_CL37_TX_CONFIG_MASK 0x08
1428 #define XGBE_AN_CL37_MII_CTRL_8BIT 0x0100
1430 #define XGBE_PMA_CDR_TRACK_EN_MASK 0x01
1431 #define XGBE_PMA_CDR_TRACK_EN_OFF 0x00
1432 #define XGBE_PMA_CDR_TRACK_EN_ON 0x01
1436 #define XGBE_PMA_PLL_CTRL_DISABLE 0x0000
1439 #define XGBE_PMA_RX_RST_0_RESET_ON 0x10
1440 #define XGBE_PMA_RX_RST_0_RESET_OFF 0x00
1451 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1455 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
1456 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1457 } while (0)
1460 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1464 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \
1466 ((0x1 << (_width)) - 1)) << (_index))); \
1467 } while (0)
1522 } while (0)
1548 } while (0)
1573 } while (0)
1631 } while (0)
1651 } while (0)
1674 } while (0)
1708 } while (0)
1742 } while (0)
1750 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \
1751 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff)))
1757 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \
1758 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val)))
1766 } while (0)