Lines Matching +full:cts +full:- +full:override
1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
62 /* Shadow copies with read-and-clear access */
148 #define AR_D0_LCL_IFS 0x1040 /* DCU-specific IFS settings */
149 #define AR_D1_LCL_IFS 0x1044 /* DCU-specific IFS settings */
150 #define AR_D2_LCL_IFS 0x1048 /* DCU-specific IFS settings */
151 #define AR_D3_LCL_IFS 0x104c /* DCU-specific IFS settings */
152 #define AR_D4_LCL_IFS 0x1050 /* DCU-specific IFS settings */
153 #define AR_D5_LCL_IFS 0x1054 /* DCU-specific IFS settings */
154 #define AR_D6_LCL_IFS 0x1058 /* DCU-specific IFS settings */
155 #define AR_D7_LCL_IFS 0x105c /* DCU-specific IFS settings */
156 #define AR_D8_LCL_IFS 0x1060 /* DCU-specific IFS settings */
157 #define AR_D9_LCL_IFS 0x1064 /* DCU-specific IFS settings */
184 #define AR_D0_MISC 0x1100 /* Misc DCU-specific settings */
185 #define AR_D1_MISC 0x1104 /* Misc DCU-specific settings */
186 #define AR_D2_MISC 0x1108 /* Misc DCU-specific settings */
187 #define AR_D3_MISC 0x110c /* Misc DCU-specific settings */
188 #define AR_D4_MISC 0x1110 /* Misc DCU-specific settings */
189 #define AR_D5_MISC 0x1114 /* Misc DCU-specific settings */
190 #define AR_D6_MISC 0x1118 /* Misc DCU-specific settings */
191 #define AR_D7_MISC 0x111c /* Misc DCU-specific settings */
192 #define AR_D8_MISC 0x1120 /* Misc DCU-specific settings */
193 #define AR_D9_MISC 0x1124 /* Misc DCU-specific settings */
208 /* MAC DCU-global IFS settings */
238 #define AR_STA_ID0 0x8000 /* station ID0 - low 32 bits */
239 #define AR_STA_ID1 0x8004 /* station ID1 - upper 16 bits */
242 #define AR_SLOT_TIME 0x8010 /* Time-out after a collision */
243 #define AR_TIME_OUT 0x8014 /* ACK & CTS time-out */
275 #define AR_CR_SWI 0x00000040 /* One-shot software interrupt */
283 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
333 /* Maui2/Spirit only - reserved on Oahu */
334 #define AR_RXCFG_ZLFDMA 0x00000010 /* Enable DMA of zero-length frame */
382 #define AR_ISR_MIB 0x00001000 /* MIB interrupt - see MIBC */
385 #define AR_ISR_RXKCM 0x00008000 /* Key-cache miss interrupt */
398 #define AR_ISR_S0_QCU_TXOK_M 0x000003FF /* Mask for TXOK (QCU 0-9) */
399 #define AR_ISR_S0_QCU_TXDESC_M 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
401 #define AR_ISR_S1_QCU_TXERR_M 0x000003FF /* Mask for TXERR (QCU 0-9) */
402 #define AR_ISR_S1_QCU_TXEOL_M 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
404 #define AR_ISR_S2_QCU_TXURN_M 0x000003FF /* Mask for TXURN (QCU 0-9) */
410 #define AR_ISR_S3_QCU_QCBROVF_M 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
411 #define AR_ISR_S3_QCU_QCBRURN_M 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
413 #define AR_ISR_S4_QCU_QTRIG_M 0x000003FF /* Mask for QTRIG (QCU 0-9) */
429 #define AR_IMR_MIB 0x00001000 /* MIB interrupt - see MIBC */
432 #define AR_IMR_RXKCM 0x00008000 /* Key-cache miss interrupt */
445 #define AR_IMR_S0_QCU_TXOK 0x000003FF /* Mask for TXOK (QCU 0-9) */
447 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
448 #define AR_IMR_S0_QCU_TXDESC_S 16 /* Shift for TXDESC (QCU 0-9) */
450 #define AR_IMR_S1_QCU_TXERR 0x000003FF /* Mask for TXERR (QCU 0-9) */
452 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
453 #define AR_IMR_S1_QCU_TXEOL_S 16 /* Shift for TXEOL (QCU 0-9) */
455 #define AR_IMR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
462 #define AR_IMR_S3_QCU_QCBROVF_M 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
463 #define AR_IMR_S3_QCU_QCBRURN_M 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
464 #define AR_IMR_S3_QCU_QCBRURN_S 16 /* Shift for QCBRURN (QCU 0-9) */
466 #define AR_IMR_S4_QCU_QTRIG_M 0x000003FF /* Mask for QTRIG (QCU 0-9) */
469 /* Interrupt status registers (read-and-clear access, secondary shadow copies) */
472 #define AR_NUM_QCU 10 /* Only use QCU 0-9 for forward QCU compatibility */
484 #define AR_Q_TXE_M 0x000003FF /* Mask for TXE (QCU 0-9) */
486 #define AR_Q_TXD_M 0x000003FF /* Mask for TXD (QCU 0-9) */
499 #define AR_Q_ONESHOTARM_SC_M 0x0000FFFF /* Mask for MAC_Q_ONESHOTARM_SC (QCU 0-15) */
502 #define AR_Q_ONESHOTARM_CC_M 0x0000FFFF /* Mask for MAC_Q_ONESHOTARM_CC (QCU 0-15) */
510 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */
528 #define AR_Q_RDYTIMESHDN_M 0x000003FF /* Mask for ReadyTimeShutdown status (QCU 0-9) */
543 #define AR_D_QCUMASK_M 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
582 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame */
586 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Post-frame backoff disable */
604 #define AR_D_TXPSE_CTRL_M 0x000003FF /* Mask of DCUs to pause (DCUs 0-9) */
614 #define AR_RC_PCI 0x00000010 /* PCI-core reset */
628 * However, these have been pre-shifted with AR_SCR_SLE_S. The
743 #define AR_EEPROM_CFG_SIZE_M 0x00000003 /* Mask for EEPROM size determination override */
762 #define AR_STA_ID1_ADHOC 0x00020000 /* Device is ad-hoc */
763 #define AR_STA_ID1_PWR_SAV 0x00040000 /* Power save reporting in self-generated frames */
769 #define AR_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mb/s rate for ACK & CTS */
770 #define AR_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate for ACK & CTS */
780 #define AR_TIME_OUT_ACK 0x00001FFF /* Mask for ACK time-out */
781 #define AR_TIME_OUT_ACK_S 0 /* Shift for ACK time-out */
782 #define AR_TIME_OUT_CTS 0x1FFF0000 /* Mask for CTS time-out */
783 #define AR_TIME_OUT_CTS_S 16 /* Shift for CTS time-out */
831 #define AR_DIAG_SW_DIS_CTS 0x00000004 /* disable CTS generation */
841 #define AR_DIAG_SW_FRAME_NV0 0x00020000 /* accept frames of non-zero protocol version */
848 #define AR_KEYTABLE_KEY0(n) (AR_KEYTABLE(n) + 0) /* key bit 0-31 */
849 #define AR_KEYTABLE_KEY1(n) (AR_KEYTABLE(n) + 4) /* key bit 32-47 */
850 #define AR_KEYTABLE_KEY2(n) (AR_KEYTABLE(n) + 8) /* key bit 48-79 */
851 #define AR_KEYTABLE_KEY3(n) (AR_KEYTABLE(n) + 12) /* key bit 80-95 */
852 #define AR_KEYTABLE_KEY4(n) (AR_KEYTABLE(n) + 16) /* key bit 96-127 */
859 #define AR_KEYTABLE_MAC0(n) (AR_KEYTABLE(n) + 24) /* MAC address 1-32 */
860 #define AR_KEYTABLE_MAC1(n) (AR_KEYTABLE(n) + 28) /* MAC address 33-47 */