Lines Matching full:atu
1370 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */
2644 ** ATU Interface Configuration Header Format
2645 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface.
2649 ** | ATU Device ID | Vendor ID …
2653 ** | ATU Class Code | Revision ID …
2657 ** | Inbound ATU Base Address 0 …
2659 ** | Inbound ATU Upper Base Address 0 …
2661 ** | Inbound ATU Base Address 1 …
2663 ** | Inbound ATU Upper Base Address 1 …
2665 ** | Inbound ATU Base Address 2 …
2667 ** | Inbound ATU Upper Base Address 2 …
2671 ** | ATU Subsystem ID | ATU Subsystem Vendor ID …
2685 ** ATU Vendor ID Register - ATUVID
2688 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Inte…
2697 ** ATU Device ID Register - ATUDID
2700 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the …
2707 ** ATU Command Register - ATUCMD
2711 … Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal.
2715 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus.
2717 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not a…
2719 ** ATU inserts 2 clock cycles of address stepping for Conv…
2721 ** 06 0 2 Parity Error Response - When set, the ATU takes normal …
2723 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not s…
2725 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may …
2726 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI…
2727 ** 03 0 2 Special Cycle Enable - The ATU interface does not respo…
2729 ** 02 0 2 Bus Master Enable - The ATU interface can act as a mast…
2732 ** When operating in the PCI-X mode, ATU initiates a split…
2734 ** 01 0 2 Memory Enable - Controls the ATU interface��s response …
2735 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus.
2736 ** 00 0 2 I/O Space Enable - Controls the ATU interface response …
2743 ** ATU Status Register - ATUSR (Sheet 1 of 2)
2746 … Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even
2748 ** �E Write Data Parity Error when the ATU is a target (inbound write).
2749 ** �E Read Data Parity Error when the ATU is a requester (outbound read).
2750 …ribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU).
2751 … 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU.
2752 … Master Abort - set when a transaction initiated by the ATU PCI master interfac…
2753 ** or when the ATU receives a Master Abort Split Completio…
2754 … Target Abort (master) - set when a transaction initiated by the ATU PCI master interfac…
2755 ** abort or when the ATU receives a Target Abort Split Com…
2756 ** 11 0 2 Target Abort (target) - set when the ATU interface, act…
2765 ** The ATU interface uses Medium timing.
2766 ** 08 0 2 Master Parity Error - The ATU interface sets this bit u…
2767 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted.
2768 ** �E And the ATU acted as the requester
2771 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
2775 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-t…
2781 ** 03 0 Interrupt Status - reflects the state of the ATU interr…
2783 ** 0=ATU interrupt signal deasserted.
2784 ** 1=ATU interrupt signal asserted.
2786 ** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU
2794 ** ATU Revision ID Register - ATURID
2797 ** 07:00 00H ATU Revision - identifies the 80331 revision number.
2803 ** ATU Class Code Register - ATUCCR
2814 ** ATU Cacheline Size Register - ATUCLSR
2817 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline siz…
2823 ** ATU Latency Timer Register - ATULT
2836 ** ATU Header Type Register - ATUHTR
2840 … PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface
2847 ** ATU BIST Register - ATUBISTR
2849 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is
2854 … BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enab…
2872 ** ATU Base Registers and Associated Limit Registers
2875 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines t…
2876 ** Inbound ATU Upper Base Address Register 0 N/A Together …
2877 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines i…
2878 ** Inbound ATU Upper Base Address Register 1 N/A Together …
2879 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines t…
2880 ** Inbound ATU Upper Base Address Register 2 N/A Together …
2881 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines t…
2882 ** Inbound ATU Upper Base Address Register 3 N/A Together …
2886 ** ATU Inbound Window 1 is not a translate window.
2887 ** The ATU does not claim any PCI accesses that fall within this range.
2889 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the …
2895 ** Inbound ATU Base Address Register 0 - IABAR0
2897 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Add…
2899 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a transla…
2927 ** The ATU does not occupy I/O sp…
2936 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0
2954 ** Inbound ATU Base Address Register 1 - IABAR1
2956 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Addre…
2958 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process an…
2960 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written fr…
2983 ** The ATU does not occupy I/O sp…
2990 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1
2994 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any …
2997 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written
3012 ** Inbound ATU Base Address Register 2 - IABAR2
3014 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Add…
3016 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a transla…
3044 ** The ATU does not occupy I/O sp…
3051 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2
3072 ** ATU Subsystem Vendor ID Register - ASVIR
3081 ** ATU Subsystem ID Register - ASIR
3104 ** ATU Capabilities Pointer Register - ATU_CAP_PTR
3121 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0
3126 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their
3168 ** ATU Interrupt Line Register - ATUILR
3180 ** ATU Interrupt Pin Register - ATUIPR
3183 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU …
3189 ** ATU Minimum Grant Register - ATUMGNT
3198 ** ATU Maximum Latency Register - ATUMLAT
3210 ** The ATU allows external PCI bus initiators to directly access the internal bus.
3215 ** within the address windows defined for the inbound ATU.
3220 ** The ATU uses the following registers in inbound address window 0 translation:
3221 ** �E Inbound ATU Base Address Register 0
3222 ** �E Inbound ATU Limit Register 0
3223 ** �E Inbound ATU Translate Value Register 0
3224 ** The ATU uses the following registers in inbound address window 2 translation:
3225 ** �E Inbound ATU Base Address Register 2
3226 ** �E Inbound ATU Limit Register 2
3227 ** �E Inbound ATU Translate Value Register 2
3228 ** The ATU uses the following registers in inbound address window 3 translation:
3229 ** �E Inbound ATU Base Address Register 3
3230 ** �E Inbound ATU Limit Register 3
3231 ** �E Inbound ATU Translate Value Register 3
3247 ** the PCI Address is claimed by the Inbound ATU.
3252 …d PCI address is detected as being within the inbound translation window and is claimed by the ATU.
3254 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for …
3265 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Va…
3269 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data p…
3295 ** Inbound ATU Limit Register 0 - IALR0
3320 ** Inbound ATU Translate Value Register 0 - IATVR0
3322 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to
3324 ** inbound ATU address translation.
3327 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to…
3329 ** The default address allows the ATU to access the internal 80331 memory-mapped registers.
3338 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines
3357 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the
3369 ** Inbound ATU Limit Register 1 - IALR1
3378 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does
3380 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1,
3392 ** Inbound ATU Limit Register 2 - IALR2
3422 ** Inbound ATU Translate Value Register 2 - IATVR2
3424 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to
3426 ** inbound ATU address translation.
3429 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to…
3431 ** The default address allows the ATU to access the internal 80331 ** ** memory-m…
3442 ** result of the outbound ATU address translation.
3458 ** driven on the PCI bus as a result of the outbound ATU address translation.
3475 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
3492 ** driven on the PCI bus as a result of the outbound ATU address translation.
3509 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
3526 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host
3536 ** ATU Configuration Register - ATUCR
3538 ** The ATU Configuration Register controls the outbound address translation for address translation
3540 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST
3545 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish …
3547 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data…
3551 ** the ATU forwards internal bus cycles with an address between 0000.0040H and
3555 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR…
3557 … 0 2 ATU Discard Timer Status - when set, one of the 4 discard tim…
3561 ** when the ATU detects that SERR# was asserted. When clear,
3563 … Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU.
3568 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interr…
3572 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound ad…
3573 ** When cleared, disables the outbound ATU.
3590 …Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU).
3657 ** �E All current PCI transactions being mastered by the ATU completes,
3658 ** and the ATU master interfaces
3661 ** �E All current transactions being slaved by the ATU on either the PCI bus
3663 ** completes, and the ATU target interfaces proceeds to an idle state.
3669 ** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32
3673 ** The ATU hardware responds the same as in Conventional PCI-X mode.
3676 ** ATU is either waiting to receive (Outbound Request) or initiate
3685 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional …
3686 ** however the user is now assured that the ATU no longer has any pending inbound or outbound spl…
3690 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate
3727 ** ATU Interrupt Status Register - ATUISR
3729 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU
3732 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Regis…
3735 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits i…
3743 ** this bit results in the assertion of the ATU Configure Register Write Interrupt.
3745 … 0 2 ATU Configuration Write - This bit is set when a PCI bus configuratio…
3746 … When set, this bit results in the assertion of the ATU Configure Register …
3747 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is …
3749 …rs deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU
3755 … Power State Transition - When the Power State Field of the ATU Power Management Co…
3756 ** Register is written to transition the ATU function Power State from D0 to D3, D0 …
3757 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set.
3758 … P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU.
3761 ** �E Write Data Parity Error when the ATU is a target (inbound write).
3762 ** �E Read Data Parity Error when the ATU is an initiator (outbound read).
3764 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST S…
3765 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt…
3769 ** of the ATU Configure Register Write Interrupt.
3770 … Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initia…
3772 … P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU.
3773 … PCI Master Abort - set when a transaction initiated by the ATU PCI initiator inter…
3774 … PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interfac…
3775 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface,…
3776 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU…
3778 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted.
3779 ** �E And the ATU acted as the requester for the operation in which the error occurr…
3781 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
3788 ** ATU Interrupt Mask Register - ATUIMR
3790 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts
3791 ** generated by the ATU.
3796 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR regist…
3801 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configur…
3802 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3…
3805 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Control…
3806 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs t…
3811 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Mess…
3815 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in…
3820 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transi…
3821 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0.
3824 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the…
3825 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of th…
3828 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the settin…
3829 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the…
3832 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another ma…
3833 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the sett…
3834 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set.
3837 … ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of b…
3841 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls …
3842 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR bein…
3845 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls t…
3846 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set.
3849 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU …
3854 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response…
3861 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2…
3869 ** Inbound ATU Base Address Register 3 - IABAR3
3871 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Add…
3873 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a transla…
3904 ** The ATU does not occupy I/O sp…
3911 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3
3931 ** Inbound ATU Limit Register 3 - IALR3
3961 ** Inbound ATU Translate Value Register 3 - IATVR3
3963 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to
3965 ** inbound ATU address translation.
3968 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to…
3969 … This value must be 64-bit aligned on the internal bus. The default address allows the ATU to
4009 ** within the ATU configuration space.
4113 ** information on the capabilities of the ATU function related to power management.
4203 ** This register controls various modes and features of ATU and Message Unit when operating in the
4239 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message
4273 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a …
4327 ** �E The ATU claims the PCI read transaction when the PCI address is within the inbound
4328 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base
4333 ** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a
4354 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target
4356 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the
4363 ** �X An internal bus Target Abort was detected. The ATU generates a Split Completion
4367 ** �X An internal bus Master Abort was detected. The ATU generates a Split Completion
4372 ** bus, the ATU PCI slave interface waits with no premature disconnects.
4377 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a
4380 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates
4383 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending
4384 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this
4387 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the
4390 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer
4400 ** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in
4402 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU
4412 ** �X The full byte count requested by the ATU read request is received. The ATU internal bus
4418 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split
4424 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus.
4427 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to
4432 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain
4434 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to
4438 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For
4439 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read
4441 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return
4443 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read
4454 ** �E The ATU claims the PCI write transaction when the PCI address is within the inbound
4455 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper
4474 … satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU
4475 ** internal master interface. The ATU does not insert target wait states nor do data merging on t…
4478 ** configuration write transactions are processed as split transactions. The ATU generates a Split
4482 ** The ATU handles such transactions as independent transactions.
4484 ** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry
4492 ** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When
4499 ** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator
4525 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
4526 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split
4527 ** completion transaction, the ATU attempts to complete the transaction normally and no further
4536 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
4537 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR#
4538 ** assertion during the split completion transaction, the ATU attempts to complete the transaction
4547 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X m…
4553 ** As a target, the ATU may encounter this error when operating in the PCI-X mode.
4564 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
4565 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on
4566 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the w…
4568 ** the given constraints are taken by the ATU:
4572 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4574 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4583 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
4587 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the
4591 ** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the
4593 ** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status
4595 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for
4597 ** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY#
4600 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the
4603 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4605 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4608 ** bus and the ATU returns the status from the internal bus, completing the transaction.
4611 ** returned is normal completion) the ATU performs the following actions with the given constraint…
4612 ** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY#
4615 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4617 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4622 ** Data parity errors occurring during configuration write operations received by the ATU may cause
4624 ** occurs, the ATU accepts the write data and complete with a Split Response Termination.
4625 ** Specifically, the following actions with the given constraints are then taken by the ATU:
4628 ** the bus. When the ATU asserts PERR#, additional actions is taken:
4630 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus
4636 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4638 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4648 ** As a target, the ATU may encounter this error when operating in the PCI-X mode.
4649 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert
4651 ** ATU accepts the data and complete normally. Specifically, the following actions with the given
4652 ** constraints are taken by the ATU:
4655 ** is set. When the ATU asserts PERR#, additional actions is taken:
4657 ** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the
4661 ** When the ATU asserts SERR#, additional actions is taken:
4663 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the
4665 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the
4669 ** When the ATU sets this bit, additional actions is taken:
4670 ** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the
4673 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4675 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4692 ** 1.Inbound ATU Base Address Register 0 (IABAR0)
4693 ** 2.Inbound ATU Limit Register 0 (IALR0)
4694 ** All of the Messaging Unit errors are reported in the same manner as ATU errors.
4711 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space
4791 …MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU).
4793 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Addr…
4796 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status in…
4797 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Con…
4798 ** The Messaging Unit reports all PCI errors in the ATU Status Register.
4853 … interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Regis…
5324 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Registe…
5325 ** to Inbound ATU Translate Value Registe…
5345 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation…
5504 ** by adding the Index Address Register to the Inbound ATU Translate Value Register.