Lines Matching +full:rx +full:- +full:tx

3  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
134 /* get rx dma good octet counter lsw */
137 /* get rx dma good packet counter lsw */
140 /* get tx dma good octet counter lsw */
143 /* get tx dma good packet counter lsw */
146 /* get rx dma good octet counter msw */
149 /* get rx dma good packet counter msw */
152 /* get tx dma good octet counter msw */
155 /* get tx dma good packet counter msw */
158 /* get  rx lro coalesced packet count lsw */
161 /* get msm rx errors counter register */
164 /* get msm rx unicast frames counter register */
167 /* get msm rx multicast frames counter register */
170 /* get msm rx broadcast frames counter register */
173 /* get msm rx broadcast octets counter register 1 */
176 /* get msm rx unicast octets counter register 0 */
179 /* get rx dma statistics counter 7 */
182 /* get msm tx errors counter register */
185 /* get msm tx unicast frames counter register */
188 /* get msm tx multicast frames counter register */
191 /* get msm tx broadcast frames counter register */
194 /* get msm tx multicast octets counter register 1 */
197 /* get msm tx broadcast octets counter register 1 */
200 /* get msm tx unicast octets counter register 0 */
206 /** \brief Set Tx Register Reset Disable
207 …egisterResetDisable 1 = Disable the S/W reset to MAC-PHY registers, 0 = Enable the S/W reset to MA…
212 /** \brief Get Tx Register Reset Disable
213 *   \return 1 = Disable the S/W reset to MAC-PHY registers, 0 = Enable the S/W reset to MAC-PHY reg…
225 /* set interrupt mapping enable rx */
226 void itr_irq_map_en_rx_set(struct aq_hw *aq_hw, u32 irq_map_en_rx, u32 rx);
228 /* set interrupt mapping enable tx */
229 void itr_irq_map_en_tx_set(struct aq_hw *aq_hw, u32 irq_map_en_tx, u32 tx);
231 /* set interrupt mapping rx */
232 void itr_irq_map_rx_set(struct aq_hw *aq_hw, u32 irq_map_rx, u32 rx);
234 /* set interrupt mapping tx */
235 void itr_irq_map_tx_set(struct aq_hw *aq_hw, u32 irq_map_tx, u32 tx);
295 /* set rx dca enable */
298 /* set rx dca mode */
301 /* set rx descriptor data buffer size */
306 /* set rx descriptor dca enable */
310 /* set rx descriptor enable */
314 /* set rx descriptor header splitting */
319 /* get rx descriptor head pointer */
322 /* set rx descriptor length */
326 /* set rx descriptor write-back interrupt enable */
330 /* set rx header dca enable */
334 /* set rx payload dca enable */
337 /* set rx descriptor header buffer size */
342 /* set rx descriptor reset */
363 /* set rx dma descriptor base address lsw */
368 /* set rx dma descriptor base address msw */
373 /* get rx dma descriptor status register */
376 /* set rx dma descriptor tail pointer register */
380 /* get rx dma descriptor tail pointer register */
383 /* set rx filter multicast filter mask register */
387 /* set rx filter multicast filter register */
391 /* set rx filter rss control register 1 */
395 /* Set RX Filter Control Register 2 */
398 /* Set RX Interrupt Moderation Control Register */
403 /* set tx dma debug control */
406 /* set tx dma descriptor base address lsw */
411 /* set tx dma descriptor base address msw */
416 /* set tx dma descriptor tail pointer register */
421 /* get tx dma descriptor tail pointer register */
424 /* Set TX Interrupt Moderation Control Register */
446 /* set rx traffic class mode */
450 /* set rx buffer enable */
453 /* set rx buffer high threshold (per tc) */
458 /* set rx buffer low threshold (per tc) */
463 /* set rx flow control mode */
466 /* set rx packet buffer size (per tc) */
471 /* set rx xoff enable (per tc) */
518 /* set user-priority tc mapping */
585 /* Set VLAN RX queue assignment enable */
589 /* Set VLAN RX queue */
597 /* set  ethertype user-priority enable */
602 /* set  ethertype rx queue enable */
607 /* set ethertype rx queue */
611 /* set ethertype user-priority */
651 /* set L3/L4 rx queue enable */
660 /* set L3/L4 rx queue */
701 /* set  ethertype user-priority enable */
705 /* set  ethertype rx queue enable */
709 /* set ethertype rx queue */
713 /* set ethertype user-priority */
752 /* set L3/L4 rx queue enable */
761 /* set L3/L4 rx queue */
779 /* set rx descriptor vlan stripping */
824 /* rx */
826 /* set rx register reset disable */
838 /* set tx descriptor enable */
841 /* set tx dca enable */
844 /* set tx dca mode */
847 /* set tx descriptor dca enable */
850 /* get tx descriptor head pointer */
853 /* set tx descriptor length */
857 /* set tx descriptor write-back interrupt enable */
861 /* set tx descriptor write-back threshold */
885 /* set tx buffer enable */
888 /* set tx tc mode */
891 /* set tx buffer high threshold (per tc) */
896 /* set tx buffer low threshold (per tc) */
901 /* set tx dma system loopback enable */
904 /* set tx packet buffer size (per tc) */
908 /* toggle rdm rx dma descriptor cache init */
911 /* set tx path pad insert enable */
924 /* set tx pkt system loopback enable */
929 /* set tx packet scheduler data arbitration mode */
933 /* set tx packet scheduler descriptor rate current time reset */
937 /* set tx packet scheduler descriptor rate limit */
941 /* set tx packet scheduler descriptor tc arbitration mode */
945 /* set tx packet scheduler descriptor tc max credit */
950 /* set tx packet scheduler descriptor tc weight */
955 /* set tx packet scheduler descriptor vm arbitration mode */
959 /* set tx packet scheduler tc data max credit */
964 /* set tx packet scheduler tc data weight */
969 /* tx */
971 /* set tx register reset disable */
1031 /* clear command for filter l3-l4 */
1048 /* set command for filter l3-l4 */
1089 /* Set VLAN RX queue assignment enable */
1093 /* Set VLAN RX queue */
1101 /* set  ethertype user-priority enable */
1106 /* set  ethertype rx queue enable */
1111 /* set ethertype rx queue */
1115 /* set ethertype user-priority */
1155 /* set L3/L4 rx queue enable */
1164 /* set L3/L4 rx queue */